msp430F5438+CC2520通信

硬件初始化包括時(shí)鐘的初始化，SPI初始化，UART初始化等。

以下是一個(gè)時(shí)鐘初始化的程序： MSP430F5438
// -----------------
// /|| |
// | | P7.0|-->XT1 37.768K
// --| P7.1 |-->

// | P5.2|-->XT2 16M

// | P5.3|-->
// | |

硬件連接方面，P7.0與P7.1連接晶振XTI，P5.2與P5.3連接晶振XT2。

void XT1_DCO(unsigned int flln)
{
// Initialize LFXT1
P7SEL |= 0x03; // Select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap

// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag

// Initialize DCO to 2.45MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz
UCSCTL2 = FLLD_1 + flln; // Set DCO Multiplier for 2.45MHz
// (N + 1) * FLLRef = Fdco
// (74 + 1) * 32768 = 2.45MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 2.45 MHz / 32,768 Hz = 76563= MCLK cycles for DCO to settle

__delay_cycles(76563);

// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag

}

參數(shù) flln用于設(shè)置時(shí)鐘頻率MCLK= SMCLK=flln*32.768K，ACLK=32.768K。