S3C2410中斷機制及相關寄存器介紹

1.中斷向量表

每個中斷都對應一段中斷服務程序。當中斷發(fā)生時，處理器就執(zhí)行該中斷對應的服務程序，實現(xiàn)該中斷所要求完成的任務。處理器如何找到對應的中斷服務程序呢？這就需要讀取處理器的中斷向量表。

中斷向量表其實就對應了系統(tǒng)的一段存儲區(qū)，它按照一定規(guī)律存儲了處理器中所有不同類型中斷的服務程序入口地址（又稱中斷向量）。S3C2410是基于ARM920T核，ARM920T的中斷向量表有兩種存放方式，一種是低端存放（從0x00000000處開始存放），另一種是高端存放（從0xfff000000處開始存放）。ARM920T能處理8個類型的中斷，他們分別是：

>Reset：當處理器的復位電平有效時，產(chǎn)生復位異常，程序跳轉到復位處理程序執(zhí)行。

>Undefined instruction：當處理器遇到不能處理的指令時產(chǎn)生未定義指令中斷。

>Software Interrupt：執(zhí)行SWI（軟件中斷）指令時產(chǎn)生，可用于用戶實現(xiàn)系統(tǒng)調用

>Abort (prefetch)：當處理器預取指令的地址不存在或該地址不允許當前指令訪問時，存儲器會向處理器發(fā)出中止信號，但當預取的指令被執(zhí)行時，才會產(chǎn)生指令預取中斷。

>Abort (data)：當處理器訪問的指令地址不存在或該地址不允許當前指令訪問時，產(chǎn)生數(shù)據(jù)中止中斷。

>Reserved：保留。

>IRQ：當處理器的外部中斷請求引腳有效，且CPSR的I位為0時產(chǎn)生IRQ中斷。

>FIQ：當處理器的快速中斷請求引腳有效，且CPSR的F位為0時產(chǎn)生FIQ中斷。

對應的中斷向量表如表1-1所示。

表1-1中斷向量表

一般情況下，在每個入口地址處都存放了一條跳轉指令，我們知道Uboot是用來完成系統(tǒng)的啟動加載過程的，在u-boot的/cpu/start.S文件中，就有“b reset”指令，放在0x00000000地址。系統(tǒng)上電以后，CPU將會從0x00000000處得這條指令執(zhí)行，執(zhí)行完以后，CPU會跳轉到reset標識的代碼段去執(zhí)行處理器復位程序。同樣，在系統(tǒng)運行過程中，每當有中斷發(fā)生，CPU會根據(jù)中斷類型（用中斷號標識），從內(nèi)存的0x00000000處開始查表做相應的處理。比如系統(tǒng)觸發(fā)了一個IRQ中斷，IRQ為第6號中斷，則CPU將把PC指向0x00000018地址（4*6=24= 0x00000018）處運行，該地址的指令是跳轉到“IRQ中斷服務程序”處運行。

S3C2410中斷源，如圖1-1中斷源所示：

圖1-1中斷源

INTERRUPT CONTROLLER OPERATION

F-bit and I-bit of Program Status Register (PSR)

If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller. So, the interrupt controller can receive interrupts by clearing F-bit or I-bit of the PSR to 0 and setting the corresponding bit of INTMSK to 0.

Interrupt Mode

The ARM920T has two types of Interrupt mode: FIQ or IRQ. All the interrupt sources determine which mode is used at interrupt request.

Interrupt Pending Register

The S3C2410A has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure. If interrupts are masked, the corresponding bits of the SRCPND register are set to 1. This does not cause the bit of INTPND register changed. When a pending bit of the INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method.

Interrupt Mask Register

This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.

S3C2410的中斷控制器原理如圖1-2所示。

圖1-2中斷控制器原理

由上圖可以看出S3C2410的中斷控制器主要通過幾個控制寄存器來實現(xiàn)：中斷源待決寄存器（Source Pending Register，SRCPND/SUBSRCPND）、中斷模式寄存器（Interrupt Mode Register,INTMOD）、中斷屏蔽寄存器（Interrupt Mask Register,INTMASK/INTSUBMSK）、中斷優(yōu)先級控制寄存器（IRQ PRIORITY Control Register,PRIORITY）、中斷待決寄存器（Interrupt Pending Register,INTPND）。

該圖也顯示了S3C2410的中斷處理流程：首先要有中斷源產(chǎn)生中斷，這里面有兩條路徑表示中斷源，上面一條是次級中斷源，當次級中斷產(chǎn)生后，首先在SUBSRCPND寄存器中登記，然后經(jīng)過次級屏蔽寄存器（SUBMASK）來決定這個次級中斷源所產(chǎn)生的中斷是否被屏蔽掉，被屏蔽掉的中斷將不會被執(zhí)行。次級中斷源所產(chǎn)生的中斷在經(jīng)過SUBMASK之后將會與主中斷源所產(chǎn)生的中斷匯合，然后在SRCPND寄存器中登記，再經(jīng)過主屏蔽寄存器，得出該中斷是否被送往CPU處理的決定。當然，在送往CPU處理之前，還要根據(jù)中斷模式寄存器的設置判斷一下該中斷是屬于IRQ中斷還是FIQ中斷，如果是FIQ中斷則直接觸發(fā)。如果是IRQ中斷，則還要判斷中斷的優(yōu)先級別，級別高的先執(zhí)行。

（1）中斷源待決寄存器SRCPND/ SUBSRCPND

這兩個寄存器在功能上是相同的，它們是中斷源待決寄存器。在一個中斷處理流程中，中斷信號傳進中斷控制器后首先遇到的就是SRCPND/ SUBSRCPND,這兩個寄存器的作用是用于標示出哪個中斷請求被觸發(fā)。SRCPND的有效位為32，SUBSRCPND的有效位為11，它們中的每一位分別代表一個中斷源。SRCPND為主中斷源待決寄存器，SUBSRCPND為次中斷源待決寄存器。

The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. Accordingly, this register indicates which interrupt source is waiting for the request to be serviced. Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, the SRCPND register is not affected by the priority logic of interrupt controller.

In the interrupt service routine for a specific interrupt source, the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, the interrupt controller operates as if another interrupt request came in from the same source. In other words, if a specific bit of the SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced.

The time to clear the corresponding bit depends on the users requirement. If you want to receive another valid request from the same source, you should clear the corresponding bit first, and then enable the interrupt.

You can clear a specific bit of the SRCPND register by writing a data to this register.It clears only the bit positions of the SRCPND corresponding to those set to one in the data. The bit positions corresponding tothose that are set to 0 in the data remains as they are.

SRCPND的各個位信息如表1-3所示。

表1-3 SRCPND各位信息

SRCPN寄存器中每個位的初始值皆為0。假設現(xiàn)在系統(tǒng)觸發(fā)了EINT0中斷，則第0位將被置1，代表EINT0中斷被觸發(fā)，該中斷請求即將被處理（若該中斷沒有被屏蔽的話）。SUBSRCPND情況與SRCPND相同，如表1-4所示。

表1-4 SUBSRCPND各位信息

（2）中斷模式寄存器INTMOD

該寄存器用來指定中斷源處理模式（IRQ還是FIQ），有效位為32位，每一位與SRCPND中各位相對應，若某位為0，則該位相對應的中斷按IRQ模式處理，為1則以FIQ模式進行處理，該寄存器初始化值為0x00000000,即所有中斷皆以IRQ模式進行處理。如表1-5所示。

This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt).

Note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller (you should use the FIQ mode only for the urgent interrupt). Thus,only one bit of INTMOD can be set to 1.

表1-5 INTMOD寄存器

NOTE: If an interrupt mode is set to FIQ mode in the INTMOD register, FIQ interrupt will not affect both INTPND and INTOFFSET registers. In this case, the two registers are valid only for IRQ mode interrupt source.

（3）中斷屏蔽寄存器INTMSK/ INTSUBMSK

This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.

INTMSK為主中斷屏蔽寄存器，INTSUBMSK為次中斷屏蔽寄存器。INTMSK有效位為32，INTSUBMSK有效位為11，這兩個寄存器各個位與SRCPND和SUBSRCPND分別對應。它們的作用是決定該位相應的中斷請求是否被處理。若某位被設置為1，則該位相對應的中斷產(chǎn)生后將被忽略（CPU不處理該中斷請求），設置為0則對其進行處理。這兩個寄存器初始化后的值是0xFFFFFFFF和0x7FF，既默認情況下所有的中斷都是被屏蔽的。如表1-6所示。

表1-6INTMSK寄存器

（4）PRIORITY寄存器

一個嵌入式系統(tǒng)一般有多個中斷請求源。當多個中斷源同時請求中斷時，就會存在CPU應該優(yōu)先響應哪個中斷請求源的問題，如果處理不當將會引起混亂，導致系統(tǒng)不能正常工作。通常解決這個問題的方法是根據(jù)中斷源事件的輕重緩急規(guī)定中斷源的優(yōu)先級，CPU優(yōu)先響應中斷優(yōu)先級高的中斷請求。

S3C2410的優(yōu)先級判斷分為兩級。如圖1-3所示，SRCPND寄存器對應的32個中斷源總共被分為6個組，每個組由一個ARBITER（0~5）寄存器對其進行管理。中斷必須先由所屬組的ARBITER（0~5）進行第一次優(yōu)先級判斷（第一級判斷）后再發(fā)往ARBITER6進行最終的判斷（第二級判斷）。ARBITER（0~5）這六個組的優(yōu)先級已經(jīng)固定，由ARBITER0控制的組優(yōu)先級最高，其次是ARBITER1, ARBITER2, ARBITER3, ARBITER4, ARBITER5。但是每個組中的各個中斷的優(yōu)先級是可以控制的，我們只需要設置PRIORITY的相應位。

圖1-3 Priority Generating Block

INTERRUPT PRIORITY

Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows:

— If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5.

— If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5.

— If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5.

— If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5.

Note that REQ0 of an arbiter always has the highest priority, and REQ5 has the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 to REQ4.

Here,if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, making the arbiter to operate in the fixed priority mode (note that even in this mode, we can reconfigure the priority by manually changing the ARB_SEL bits). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to put REQ1 into the lowest priority. The detailed rules of ARB_SEL change are as follows:

— If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all.

— If REQ1 is serviced, ARB_SEL bits are changed to 01b.

— If REQ2 is serviced, ARB_SEL bits are changed to 10b.

— If REQ3 is serviced, ARB_SEL bits are changed to 11b.

— If REQ4 is serviced, ARB_SEL bits are changed to 00b.

表1-7 PRIORITY寄存器

表1-7是PRIORITY寄存器各個位的參數(shù)表。從表上我們可以知道PRIORITY寄存器內(nèi)部各個位被分為兩種類型，一種是ARB_MODE,另一種為ARB_SEL, ARB_MODE類型有5組，分別對應ARBITER（2~6），ARB_SEL類型有7組，分別對應ARBITER（0~6）。

以ARBITER2為例，我們來看一下PRIORITY寄存器中ARB_SEL, ARB_MODE之間的相互關系。首先我們看到ARBITER2寄存器管理的該組中斷里包括了6個中斷，分別是INT_TIMER0，INT_TIMER1，INT_TIMER2，INT_TIMER3，INT_TIMER4，INT_UART2，它們的默認中斷請求號分別為REQ0，REQ1，REQ2，REQ3，REQ4，REQ5。我們先看PRIORITY寄存器中的ARB_SEL2，該參數(shù)由兩個位組成，初始值為00。從該表可以看出00定義了一個順序0-1-2-3-4-5，這個順序就是這組中斷組的優(yōu)先級排列，這個順序指明了以中斷請求號為0（REQ0）的INT_TIMER0具有最高的中斷優(yōu)先級，其次是INT_TIMER1，INT_TIMER2…。假設現(xiàn)在ARB_SEL2的值被我們設置為01。則一個新的優(yōu)先級次序將被使用，01對應的優(yōu)先級次序為0-2-3-4-1-5，從中可以看出優(yōu)先級最高和最低的中斷請求和之前沒有變化，但本來處于第2優(yōu)先級的INT_TIMER1中斷現(xiàn)在變成了第5優(yōu)先級。從ARB_SEL2被設置為00,01,10,11各個值所出現(xiàn)的情況可以看出，除了最高和最低的優(yōu)先級不變以外，其他各個中斷的優(yōu)先級其實是在做一個旋轉排列（rotate）。為了達到對各個中斷平等對待這一目標，我們可以讓優(yōu)先級次序在每個中斷請求被處理完之后自動進行一次旋轉，如何自動讓它旋轉呢？我們可以通過設置ARB_MODE2位達到這個目的，該位置1代表開啟對應中斷組的優(yōu)先級次序自動旋轉，0則為關閉，按固定的次序排列優(yōu)先級列表。

（5）中斷待決寄存器INTPND

Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority .Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.In interrupt service routine for IRQ, you can read this register to determine which interrupt source is serviced among the 32 sources.

Like the SRCPND register,this register has to be cleared in the interrupt service routine after clearing the SRCPND register. We can clear a specific bit of the INTPND register by writing a data to this register.It clears only the bit positions of the INTPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are.

INTPND的詳細信息如表1-8所示：

表1-8寄存器INTPND

表1-8是INTPND寄存器各位的詳細功能列表。不難發(fā)現(xiàn)，INTPND寄存器與SRCPND長得一模一樣，但他們在中斷處理中卻扮演著不同的角色。INTPND寄存器的每個位對應一個中斷請求，若該位被置1，則表示相應的中斷請求被觸發(fā)。說到這里你可能會發(fā)現(xiàn)它不僅和SRCPND長得一模一樣，就連功能都一樣，其實不然，他們在功能上有著重大的區(qū)別。SRCPND是中斷源待決寄存器，某個位被置1表示相應的中斷被觸發(fā)，但我們知道在同一時刻內(nèi)系統(tǒng)可以觸發(fā)若干個中斷，只要中斷被觸發(fā)了，SRCPND的相應位便被置1，也就是說SRCPND在同一時刻可以有若干位同時被置1，然而INTPND則不同，他在某一時刻只能有1個位被置1，INTPND某個位被置1，則表示CPU即將或已經(jīng)在對該位相應的中斷進行處理。于是我們可以有一個總結：SRCPND說明了有什么中斷被觸發(fā)了，INTPND說明了CPU即將或已經(jīng)在對某一個中斷進行處理。

每當某一個中斷被處理完之后，我們必須手動將SRCPND/SUBSRCPND , INTPND三個寄存器中與該中斷相應的位由1設置為0。

（6）中斷偏移寄存器INTOFFSET

INTOFFSET寄存器的功能很簡單，它用于表明哪個中斷正在被處理。表1-9是該寄存器各位詳細功能列表：若當前INT_TIMER0被觸發(fā)了，則該寄存器的值為10，以此類推。

表1-9 INTOFFSET寄存器