ucOS學(xué)習(xí)筆記(6)——一步一步移植ucOS到STM32
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今天早上開始寫了幾個基本的設(shè)備驅(qū)動，同時編寫了兩個簡單的測試任務(wù)。其間出現(xiàn)幾個問題。
第一個問題是代碼編譯能通過，但是下載到板子上就是跑不動，根本運行不到main函數(shù)，估計是初始化系統(tǒng)部分存在一些問題，我也沒有深入研究直接將stm32官方的stm32f10x_vector.s和現(xiàn)在的init.s整合得到以下的系統(tǒng)初始化代碼，該代碼能夠保證測試任務(wù)LED流水燈正常運行。
; If you need to use external SRAM mounted on STM3210E-EVAL board as data memory,
; change the following define value to 1 (or choose ENABLE in Configuration Wizard window)
;//
DATA_IN_ExtSRAM EQU 0
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;//
;//
;//
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; If you need to use external SRAM mounted on STM3210E-EVAL board as data memory
; and internal SRAM for Stack, uncomment the following line and comment the line above
;__initial_sp EQU 0x20000000 + Stack_Size ; "Use MicroLIB" must be checked in
; the Project->Options->Target window
; Amount of memory (in bytes) allocated for Heap
; Tailor this value to your application needs
;//
;//
;//
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
THUMB
PRESERVE8
; Import exceptions handlers
IMPORT OS_CPU_SysTickHandler
IMPORT OS_CPU_PendSVHandler
;*******************************************************************************
; Fill-up the Vector Table entries with the exceptions ISR address
;*******************************************************************************
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors
DCD __initial_sp ; 0, SP start value.
DCD Reset_Handler ; 1, PC start value.
DCD App_NMI_ISR ; 2, NMI
DCD App_Fault_ISR ; 3, Hard Fault
DCD App_Spurious_ISR ; 4, Memory Management
DCD App_Spurious_ISR ; 5, Bus Fault
DCD App_Spurious_ISR ; 6, Usage Fault
DCD 0 ; 7, Reserved
DCD 0 ; 8, Reserved
DCD 0 ; 9, Reserved
DCD 0 ; 10, Reserved
DCD App_Spurious_ISR ; 11, SVCall
DCD App_Spurious_ISR ; 12, Debug Monitor
DCD App_Spurious_ISR ; 13, Reserved
DCD OS_CPU_PendSVHandler ; 14, PendSV Handler
DCD OS_CPU_SysTickHandler ; 15, uC/OS-II Tick ISR Handler
DCD App_Spurious_ISR ; 16, INTISR[ 0], Window Watchdog
DCD App_Spurious_ISR ; 17, INTISR[ 1] PVD through EXTI Line Detection
DCD App_Spurious_ISR ; 18, INTISR[ 2] Tamper Interrupt
DCD App_Spurious_ISR ; 19, INTISR[ 3] RTC Global Interrupt
DCD App_Spurious_ISR ; 20, INTISR[ 4] FLASH Global Interrupt
DCD App_Spurious_ISR ; 21, INTISR[ 5] RCC Global Interrupt
DCD App_Spurious_ISR ; 22, INTISR[ 6] EXTI Line0 Interrupt
DCD App_Spurious_ISR ; 23, INTISR[ 7] EXTI Line1 Interrupt
DCD App_Spurious_ISR ; 24, INTISR[ 8] EXTI Line2 Interrupt
DCD App_Spurious_ISR ; 25, INTISR[ 9] EXTI Line3 Interrupt
DCD App_Spurious_ISR ; 26, INTISR[ 10] EXTI Line4 Interrupt
DCD App_Spurious_ISR ; 27, INTISR[ 11] DMA Channel1 Global Interrupt
DCD App_Spurious_ISR ; 28, INTISR[ 12] DMA Channel2 Global Interrupt
DCD App_Spurious_ISR ; 29, INTISR[ 13] DMA Channel3 Global Interrupt
DCD App_Spurious_ISR ; 30, INTISR[ 14] DMA Channel4 Global Interrupt
DCD App_Spurious_ISR ; 31, INTISR[ 15] DMA Channel5 Global Interrupt
DCD App_Spurious_ISR ; 32, INTISR[ 16] DMA Channel6 Global Interrupt
DCD App_Spurious_ISR ; 33, INTISR[ 17] DMA Channel7 Global Interrupt
DCD App_Spurious_ISR ; 34, INTISR[ 18] ADC Global Interrupt
DCD App_Spurious_ISR ; 35, INTISR[ 19] USB High Priority / CAN TX Interrupts
DCD App_Spurious_ISR ; 36, INTISR[ 20] USB Low Priority / CAN RX0 Interrupts
DCD App_Spurious_ISR ; 37, INTISR[ 21] CAN RX1 Interrupt
DCD App_Spurious_ISR ; 38, INTISR[ 22] CAN SCE Interrupt
DCD App_Spurious_ISR ; 39, INTISR[ 23] EXTI Line[9:5] Interrupt
DCD App_Spurious_ISR ; 40, INTISR[ 24] TIM1 Break Interrupt
DCD App_Spurious_ISR ; 41, INTISR[ 25] TIM1 Update Interrupt
DCD App_Spurious_ISR ; 42, INTISR[ 26] TIM1 Trigger & Commutation Interrupts
DCD App_Spurious_ISR ; 43, INTISR[ 27] TIM2 Global Interrupt
DCD App_Spurious_ISR ; 44, INTISR[ 28] TIM3 Global Interrupt
DCD App_Spurious_ISR ; 45, INTISR[ 29] TIM4 Global Interrupt
DCD App_Spurious_ISR ; 46, INTISR[ 30] I2C1 Event Interrupt
DCD App_Spurious_ISR ; 47, INTISR[ 31] I2C1 Error Interrupt
DCD App_Spurious_ISR ; 48, INTISR[ 32] I2C2 Event Interrupt
DCD App_Spurious_ISR ; 49, INTISR[ 33] I2C2 Error Interrupt
DCD App_Spurious_ISR ; 50, INTISR[ 34] SPI1 Global Interrupt
DCD App_Spurious_ISR ; 51, INTISR[ 35] SPI2 Global Interrupt
DCD App_Spurious_ISR ; 52, INTISR[ 36] USART1 Global Interrupt
DCD App_Spurious_ISR ; 53, INTISR[ 37] USART2 Global Interrupt
DCD App_Spurious_ISR ; 54, INTISR[ 38] USART3 Global Interrupt
DCD App_Spurious_ISR ; 55, INTISR[ 39] EXTI Line [15:10] Interrupts
DCD App_Spurious_ISR ; 56, INTISR[ 40] RTC Alarm through EXT Line Interrupt
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
DCD App_Spurious_ISR ; 57, INTISR[ 41] USB Wakeup from Suspend through EXTI Int.
AREA |.text|, CODE, READONLY
App_NMI_ISR B App_NMI_ISR
App_Fault_ISR B App_Fault_ISR
App_Spurious_ISR B App_Spurious_ISR
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler
IF DATA_IN_ExtSRAM == 1
; FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
; required, then adjust the Register Addresses
; Enable FSMC clock
LDR R0,= 0x00000114
LDR R1,= 0x40021014
STR R0,[R1]
; Enable GPIOD, GPIOE, GPIOF and GPIOG clocks
LDR R0,= 0x000001E0
LDR R1,= 0x40021018
STR R0,[R1]
; SRAM Data lines, NOE and NWE configuration
; SRAM Address lines configuration
; NOE and NWE configuration
; NE3 configuration
; NBL0, NBL1 configuration
LDR R0,= 0x44BB44BB
LDR R1,= 0x40011400
STR R0,[R1]
LDR R0,= 0xBBBBBBBB
LDR R1,= 0x40011404
STR R0,[R1]
LDR R0,= 0xB44444BB
LDR R1,= 0x40011800
STR R0,[R1]
LDR R0,= 0xBBBBBBBB
LDR R1,= 0x40011804
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40011C00
STR R0,[R1]
LDR R0,= 0xBBBB4444
LDR R1,= 0x40011C04
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40012000
STR R0,[R1]
LDR R0,= 0x44444B44
LDR R1,= 0x40012004
STR R0,[R1]
; FSMC Configuration
; Enable FSMC Bank1_SRAM Bank
LDR R0,= 0x00001011
LDR R1,= 0xA0000010
STR R0,[R1]
LDR R0,= 0x00000200
LDR R1,= 0xA0000014
STR R0,[R1]
ENDIF
IMPORT __main
LDR R0, =__main
BX R0
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE*****
第二個問題是在main函數(shù)中我啟用了統(tǒng)計任務(wù)，具體講就是用OSStatInit初始化統(tǒng)計任務(wù)，通過串口向外發(fā)送統(tǒng)計任務(wù)結(jié)果發(fā)現(xiàn)CPU使用率始終為零。最終將OSStatInit函數(shù)放在最高優(yōu)先級任務(wù)里執(zhí)行才能得到有效的CPU利用率統(tǒng)計結(jié)果為1%。至于發(fā)生該情況的原因可以參考http://blog.csdn.net/liuxp_008/archive/2007/08/16/1746499.aspx
http://blog.163.com/tianyake@yeah/blog/static/74933141201141035129678/
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