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ARM·存儲(chǔ)器配置

作者：時(shí)間：2016-11-24 來源：網(wǎng)絡(luò)

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關(guān)于配置SDRAM的這個(gè)程序，因?yàn)檠芯苛?天，所以這里最后再復(fù)習(xí)一下

首先補(bǔ)充一下基本的知識(shí)：

運(yùn)行地址->鏈接地址

在SRAM或者SDRAM中執(zhí)行程序時(shí)，PC指向這個(gè)地址，那么命令就應(yīng)該在這個(gè)地址里面；

加載地址->存儲(chǔ)地址

程序保存在NAND FLSAH中的地址

位置無關(guān)碼：B，BL，MOV

位置有關(guān)碼：LDR PC，=Label

【關(guān)于Makefile】

sdram.bin : head.S leds.c

arm-linux-gcc -c -o head.o head.S

arm-linux-gcc -c -o leds.o leds.c

arm-linux-ld -Ttext 0x30000000 head.o leds.o -o sdram_elf

arm-linux-objcopy -O binary -S sdram_elf sdram.bin

arm-linux-objdump -D -m arm sdram_elf > sdram.dis

clean: rm -f sdram.dis sdram.bin sdram_elf *.o

這里我們看到這一句“arm-linux-ld -Ttext 0x30000000 head.o leds.o -o sdram_elf ”，說明該程序是放在0x3000 0000的地址中的，由mini2440存儲(chǔ)地址可知，那里是SDRAM的首地址

【head.S】（配置SDRAM）

@*************************************************************************

@ File：head.S

@ 功能：設(shè)置SDRAM，將程序復(fù)制到SDRAM，然后跳到SDRAM繼續(xù)執(zhí)行

@*************************************************************************

.equ MEM_CTL_BASE, 0x48000000

.equ SDRAM_BASE, 0x30000000

.text

.global _start

_start:

bl disable_watch_dog @ 關(guān)閉WATCHDOG，否則CPU會(huì)不斷重啟

bl memsetup @ 設(shè)置存儲(chǔ)控制器

bl copy_steppingstone_to_sdram @ 復(fù)制代碼到SDRAM中

ldr pc, =on_sdram @ 跳到SDRAM中繼續(xù)執(zhí)行

on_sdram:

ldr sp, =0x34000000 @ 設(shè)置堆棧

bl main

halt_loop:

b halt_loop

disable_watch_dog:

@ 往WATCHDOG寄存器寫0即可

mov r1, #0x53000000

mov r2, #0x0

str r2, [r1]

mov pc, lr @ 返回

copy_steppingstone_to_sdram:

@ 將Steppingstone的4K數(shù)據(jù)全部復(fù)制到SDRAM中去

@ Steppingstone起始地址為0x00000000，SDRAM中起始地址為0x30000000

mov r1, #0

ldr r2, =SDRAM_BASE

mov r3, #4*1024

1:

ldr r4, [r1],#4 @ 從Steppingstone讀取4字節(jié)的數(shù)據(jù)，并讓源地址加4

str r4, [r2],#4 @ 將此4字節(jié)的數(shù)據(jù)復(fù)制到SDRAM中，并讓目地地址加4

cmp r1, r3 @ 判斷是否完成：源地址等于Steppingstone的未地址？

bne 1b @ 若沒有復(fù)制完，繼續(xù)

mov pc, lr @ 返回

memsetup:

@ 設(shè)置存儲(chǔ)控制器以便使用SDRAM等外設(shè)

mov r1, #MEM_CTL_BASE @ 存儲(chǔ)控制器的13個(gè)寄存器的開始地址

adrl r2, mem_cfg_val @ 這13個(gè)值的起始存儲(chǔ)地址

add r3, r1, #52 @ 13*4 = 54

1:

ldr r4, [r2], #4 @ 讀取設(shè)置值，并讓r2加4

str r4, [r1], #4 @ 將此值寫入寄存器，并讓r1加4

cmp r1, r3 @ 判斷是否設(shè)置完所有13個(gè)寄存器

bne 1b @ 若沒有寫成，繼續(xù)

mov pc, lr @ 返回

.align 4

mem_cfg_val:

@ 存儲(chǔ)控制器13個(gè)寄存器的設(shè)置值

.long 0x22011110 @ BWSCON

.long 0x00000700 @ BANKCON0

.long 0x00000700 @ BANKCON1

.long 0x00000700 @ BANKCON2

.long 0x00000700 @ BANKCON3

.long 0x00000700 @ BANKCON4

.long 0x00000700 @ BANKCON5

.long 0x00018005 @ BANKCON6

.long 0x00018005 @ BANKCON7

.long 0x008C07A3 @ REFRESH

.long 0x000000B1 @ BANKSIZE

.long 0x00000030 @ MRSRB6

.long 0x00000030 @ MRSRB7

【反匯編】

sdram_elf: file format elf32-littlearm

Disassembly of section .text:

30000000 <_start>:

30000000: eb000005 bl 3000001c

30000004: eb000010 bl 3000004c

30000008: eb000007 bl 3000002c

3000000c: e59ff090 ldr pc, [pc, #144] ; 300000a4

30000010 :

30000010: e3a0d30d mov sp, #872415232 ; 0x34000000

30000014: eb000035 bl 300000f0

30000018 :

30000018: eafffffe b 30000018

3000001c :

3000001c: e3a01453 mov r1, #1392508928 ; 0x53000000

30000020: e3a02000 mov r2, #0 ; 0x0

30000024: e5812000 str r2, [r1]

30000028: e1a0f00e mov pc, lr

3000002c :

3000002c: e3a01000 mov r1, #0 ; 0x0

30000030: e3a02203 mov r2, #805306368 ; 0x30000000

30000034: e3a03a01 mov r3, #4096 ; 0x1000

30000038: e4914004 ldr r4, [r1], #4

3000003c: e4824004 str r4, [r2], #4

30000040: e1510003 cmp r1, r3

30000044: 1afffffb bne 30000038

30000048: e1a0f00e mov pc, lr

3000004c :

3000004c: e3a01312 mov r1, #1207959552 ; 0x48000000

30000050: e28f2018 add r2, pc, #24 ; 0x18

30000054: e1a00000 nop (mov r0,r0)

30000058: e2813034 add r3, r1, #52 ; 0x34

3000005c: e4924004 ldr r4, [r2], #4

30000060: e4814004 str r4, [r1], #4

30000064: e1510003 cmp r1, r3

30000068: 1afffffb bne 3000005c

3000006c: e1a0f00e mov pc, lr

30000070 :

30000070: 22011110 .word 0x22011110

30000074: 00000700 .word 0x00000700

30000078: 00000700 .word 0x00000700

3000007c: 00000700 .word 0x00000700

30000080: 00000700 .word 0x00000700

30000084: 00000700 .word 0x00000700

30000088: 00000700 .word 0x00000700

3000008c: 00018005 .word 0x00018005

30000090: 00018005 .word 0x00018005

30000094: 008c07a3 .word 0x008c07a3

30000098: 000000b1 .word 0x000000b1

3000009c: 00000030 .word 0x00000030

300000a0: 00000030 .word 0x00000030

300000a4: 30000010 .word 0x30000010

300000a8: e1a00000 .word 0xe1a00000

300000ac: e1a00000 .word 0xe1a00000

300000b0 :

300000b0: e52db004 push {fp} ; (str fp, [sp, #-4]!)

300000b4: e28db000 add fp, sp, #0 ; 0x0

300000b8: e24dd00c sub sp, sp, #12 ; 0xc

300000bc: e50b0008 str r0, [fp, #-8]

300000c0: e51b2008 ldr r2, [fp, #-8]

300000c4: e3520000 cmp r2, #0 ; 0x0

300000c8: 03a03000 moveq r3, #0 ; 0x0

300000cc: 13a03001 movne r3, #1 ; 0x1

300000d0: e20310ff and r1, r3, #255 ; 0xff

300000d4: e2423001 sub r3, r2, #1 ; 0x1

300000d8: e50b3008 str r3, [fp, #-8]

300000dc: e3510000 cmp r1, #0 ; 0x0

300000e0: 1afffff6 bne 300000c0

300000e4: e28bd000 add sp, fp, #0 ; 0x0

300000e8: e8bd0800 pop {fp}

300000ec: e12fff1e bx lr

300000f0 :

300000f0: e92d4800 push {fp, lr}

300000f4: e28db004 add fp, sp, #4 ; 0x4

300000f8: e3a02456 mov r2, #1442840576 ; 0x56000000

300000fc: e2822010 add r2, r2, #16 ; 0x10

30000100: e3a03456 mov r3, #1442840576 ; 0x56000000

30000104: e2833010 add r3, r3, #16 ; 0x10

30000108: e5933000 ldr r3, [r3]

3000010c: e3c33bff bic r3, r3, #261120 ; 0x3fc00

30000110: e5823000 str r3, [r2]

30000114: e3a02456 mov r2, #1442840576 ; 0x56000000

30000118: e2822010 add r2, r2, #16 ; 0x10

3000011c: e3a03456 mov r3, #1442840576 ; 0x56000000

30000120: e2833010 add r3, r3, #16 ; 0x10

30000124: e5933000 ldr r3, [r3]

30000128: e3833b55 orr r3, r3, #87040 ; 0x15400

3000012c: e5823000 str r3, [r2]

30000130: e3a02456 mov r2, #1442840576 ; 0x56000000

30000134: e2822014 add r2, r2, #20 ; 0x14

30000138: e3a03456 mov r3, #1442840576 ; 0x56000000

3000013c: e2833014 add r3, r3, #20 ; 0x14

30000140: e5933000 ldr r3, [r3]

30000144: e3833e1e orr r3, r3, #480 ; 0x1e0

30000148: e5823000 str r3, [r2]

3000014c: e3a02456 mov r2, #1442840576 ; 0x56000000

30000150: e2822014 add r2, r2, #20 ; 0x14

30000154: e3a03456 mov r3, #1442840576 ; 0x56000000

30000158: e2833014 add r3, r3, #20 ; 0x14

3000015c: e5933000 ldr r3, [r3]

30000160: e3c33020 bic r3, r3, #32 ; 0x20

30000164: e5823000 str r3, [r2]

30000168: e3a00064 mov r0, #100 ; 0x64

3000016c: ebffffcf bl 300000b0

30000170: eafffff5 b 3000014c

Disassembly of section .comment:

00000000 <.comment>:

0: 43434700 movtmi r4, #14080 ; 0x3700

4: 5328203a teqpl r8, #58 ; 0x3a

8: 6372756f cmnvs r2, #465567744 ; 0x1bc00000

c: 20797265 rsbscs r7, r9, r5, ror #4

10: 202b2b47 eorcs r2, fp, r7, asr #22

14: 6574694c ldrbvs r6, [r4, #-2380]!

18: 30303220 eorscc r3, r0, r0, lsr #4

1c: 2d337138 ldfcss f7, [r3, #-224]!

20: 20293237 eorcs r3, r9, r7, lsr r2

24: 2e332e34 mrccs 14, 1, r2, cr3, cr4, {1}

28: Address 0x00000028 is out of bounds.

Disassembly of section .ARM.attributes:

00000000 <.ARM.attributes>:

0: 00002541 andeq r2, r0, r1, asr #10

4: 61656100 cmnvs r5, r0, lsl #2

8: 01006962 tsteq r0, r2, ror #18

c: 0000001b andeq r0, r0, fp, lsl r0

10: 00543405 subseq r3, r4, r5, lsl #8

14: 01080206 tsteq r8, r6, lsl #4

18: 01140412 tsteq r4, r2, lsl r4

1c: 03170115 tsteq r7, #1073741829 ; 0x40000005

20: 01190118 tsteq r9, r8, lsl r1

24: Address 0x00000024 is out of bounds.

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