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	 > 嵌入式系統(tǒng) > 設(shè)計(jì)應(yīng)用 > 啟動(dòng)過程都在這個(gè)文件的開頭描述了system_stm32f10x.c
          
    
          

          

          


	
	
	

          
	
          
		
          
			
          啟動(dòng)過程都在這個(gè)文件的開頭描述了system_stm32f10x.c
          
						
          
				作者：
				時(shí)間：2016-11-27
				來源：網(wǎng)絡(luò)
				
				
				
				
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          RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
          #ifdef STM32F10X_CL
          RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
          RCC_CFGR_PLLMULL6);
          RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
          RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
          RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
          RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
          RCC->CR |= RCC_CR_PLL2ON;
          while((RCC->CR & RCC_CR_PLL2RDY) == 0)
          {
          } 
          #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
          #else 
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
          #endif
          RCC->CR |= RCC_CR_PLLON;
          while((RCC->CR & RCC_CR_PLLRDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
          RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 
          while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
          {
          }
          }
          else
          {
          }
          }
          #elif defined SYSCLK_FREQ_36MHz
          static void SetSysClockTo36(void)
          {
          __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
          RCC->CR |= ((uint32_t)RCC_CR_HSEON);
          do
          {
          HSEStatus = RCC->CR & RCC_CR_HSERDY;
          StartUpCounter++; 
          } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
          if ((RCC->CR & RCC_CR_HSERDY) != RESET)
          {
          HSEStatus = (uint32_t)0x01;
          }
          else
          {
          HSEStatus = (uint32_t)0x00;
          } 
          if (HSEStatus == (uint32_t)0x01)
          {
          FLASH->ACR |= FLASH_ACR_PRFTBE;
          FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
          FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; 
          RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
          #ifdef STM32F10X_CL
          RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
          RCC_CFGR_PLLMULL9);
          RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
          RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
          RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
          RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
          RCC->CR |= RCC_CR_PLL2ON;
          while((RCC->CR & RCC_CR_PLL2RDY) == 0)
          {
          }
          #else 
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
          #endif
          RCC->CR |= RCC_CR_PLLON;
          while((RCC->CR & RCC_CR_PLLRDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
          RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 
          while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
          {
          }
          }
          else
          {
          }
          }
          #elif defined SYSCLK_FREQ_48MHz
          static void SetSysClockTo48(void)
          {
          __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
          RCC->CR |= ((uint32_t)RCC_CR_HSEON);
          do
          {
          HSEStatus = RCC->CR & RCC_CR_HSERDY;
          StartUpCounter++; 
          } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
          if ((RCC->CR & RCC_CR_HSERDY) != RESET)
          {
          HSEStatus = (uint32_t)0x01;
          }
          else
          {
          HSEStatus = (uint32_t)0x00;
          } 
          if (HSEStatus == (uint32_t)0x01)
          {
          FLASH->ACR |= FLASH_ACR_PRFTBE;
          FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
          FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; 
          RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
          #ifdef STM32F10X_CL
          RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
          RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
          RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
          RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
          RCC->CR |= RCC_CR_PLL2ON;
          while((RCC->CR & RCC_CR_PLL2RDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
          RCC_CFGR_PLLMULL6);
          #else 
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
          #endif
          RCC->CR |= RCC_CR_PLLON;
          while((RCC->CR & RCC_CR_PLLRDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
          RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 
          while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
          {
          }
          }
          else
          {
          }
          }
          #elif defined SYSCLK_FREQ_56MHz
          static void SetSysClockTo56(void)
          {
          __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
          RCC->CR |= ((uint32_t)RCC_CR_HSEON);
          do
          {
          HSEStatus = RCC->CR & RCC_CR_HSERDY;
          StartUpCounter++; 
          } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
          if ((RCC->CR & RCC_CR_HSERDY) != RESET)
          {
          HSEStatus = (uint32_t)0x01;
          }
          else
          {
          HSEStatus = (uint32_t)0x00;
          } 
          if (HSEStatus == (uint32_t)0x01)
          {
          FLASH->ACR |= FLASH_ACR_PRFTBE;
          FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
          FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 
          RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
          #ifdef STM32F10X_CL
          RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
          RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
          RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
          RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
          RCC->CR |= RCC_CR_PLL2ON;
          while((RCC->CR & RCC_CR_PLL2RDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
          RCC_CFGR_PLLMULL7);
          #else 
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
          #endif
          RCC->CR |= RCC_CR_PLLON;
          while((RCC->CR & RCC_CR_PLLRDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
          RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 
          while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
          {
          }
          }
          else
          {
          }
          }
          #elif defined SYSCLK_FREQ_72MHz
          static void SetSysClockTo72(void)
          {
          __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
          RCC->CR |= ((uint32_t)RCC_CR_HSEON);
          do
          {
          HSEStatus = RCC->CR & RCC_CR_HSERDY;
          StartUpCounter++; 
          } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
          if ((RCC->CR & RCC_CR_HSERDY) != RESET)
          {
          HSEStatus = (uint32_t)0x01;
          }
          else
          {
          HSEStatus = (uint32_t)0x00;
          } 
          if (HSEStatus == (uint32_t)0x01)
          {
          FLASH->ACR |= FLASH_ACR_PRFTBE;
          FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
          FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 
          RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
          RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
          #ifdef STM32F10X_CL
          RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
          RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
          RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
          RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
          RCC->CR |= RCC_CR_PLL2ON;
          while((RCC->CR & RCC_CR_PLL2RDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
          RCC_CFGR_PLLMULL9);
          #else 
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
          RCC_CFGR_PLLMULL));
          RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
          #endif
          RCC->CR |= RCC_CR_PLLON;
          while((RCC->CR & RCC_CR_PLLRDY) == 0)
          {
          }
          RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
          RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 
          while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
          {
          }
          }
          else
          {
          }
          }
          #endif
          
				
            
                
			
							
          
                
			            
          
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