STM32中斷流程處理

//IAR對所用語言（這里是C）做的一些擴(kuò)展，也就是說這里可以用擴(kuò)展的功能
#pragma language=extended#pragma segment="CSTACK"

void __iar_program_start( void );

#pragma location = ".intvec"

const intvec_elem __vector_table[] =
{
{ .__ptr = __sfe( "CSTACK" ) },
&__iar_program_start,
NMIException,
HardFaultException,
MemManageException,
BusFaultException,
UsageFaultException,
0, 0, 0, 0,
vPortSVCHandler,
DebugMonitor,
0,
xPortPendSVHandler,
xPortSysTickHandler,
WWDG_IRQHandler,
PVD_IRQHandler,
TAMPER_IRQHandler,
RTC_IRQHandler,
FLASH_IRQHandler,
RCC_IRQHandler,
EXTI0_IRQHandler,
EXTI1_IRQHandler,
EXTI2_IRQHandler,
EXTI3_IRQHandler,
EXTI4_IRQHandler,
DMAChannel1_IRQHandler,
DMAChannel2_IRQHandler,
DMAChannel3_IRQHandler,
DMAChannel4_IRQHandler,
DMAChannel5_IRQHandler,
DMAChannel6_IRQHandler,
DMAChannel7_IRQHandler,
ADC_IRQHandler,
USB_HP_CAN_TX_IRQHandler,
USB_LP_CAN_RX0_IRQHandler,
CAN_RX1_IRQHandler,
CAN_SCE_IRQHandler,
EXTI9_5_IRQHandler,
TIM1_BRK_IRQHandler,
TIM1_UP_IRQHandler,
TIM1_TRG_COM_IRQHandler,
TIM1_CC_IRQHandler,
vTimer2IntHandler,
TIM3_IRQHandler,
TIM4_IRQHandler,
I2C1_EV_IRQHandler,
I2C1_ER_IRQHandler,
I2C2_EV_IRQHandler,
I2C2_ER_IRQHandler,
SPI1_IRQHandler,
SPI2_IRQHandler,
vUARTInterruptHandler,
USART2_IRQHandler,
USART3_IRQHandler,
EXTI15_10_IRQHandler,
RTCAlarm_IRQHandler,
USBWakeUp_IRQHandler,
};

現(xiàn)在我們清楚了，這兒就是中斷向量表，每一個(gè)item對應(yīng)一個(gè)中斷或異常處理，這里item的填寫要和stm32spec中的Interrupt and exception vectors一節(jié)中的列表中的順序一致。

說道這里，又有一個(gè)問題，這個(gè)向量表是放在何處的呢？上面對.intvec的解釋可以看出是被鏈接器放到了一個(gè)地址上（這里是0x08000000，NVIC_VectTab_FLASH）。但是stm32是怎么知道這個(gè)地址的呢，也許有個(gè)默認(rèn)值，或者是就這一個(gè)固定值？）。我們在stm32f10x_nvic.c文件中發(fā)現(xiàn)下面這樣的一個(gè)函數(shù)

void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
{

assert(IS_NVIC_VECTTAB(NVIC_VectTab));
assert(IS_NVIC_OFFSET(Offset));

SCB->ExceptionTableOffset = (((u32)Offset << 0x07) & (u32)0x1FFFFF80);

SCB->ExceptionTableOffset |= NVIC_VectTab;
}

同時(shí)在example目錄下有vectortable_relocation這樣的一個(gè)例子：This example describes how to use the NVIC firmware library to set the CortexM3 vector table in a specific address other than default.

在這個(gè)例子里面就是直接調(diào)用了上面的那個(gè)函數(shù)，似乎意思很明顯了。但是SCB->ExceptionTableOffset是如何起作用的呢？

著重解釋這個(gè)問題，先看一組定義：【stm32f10x_map.b】

#define SCS_BASE((u32)0xE000E000)

#define SysTick_BASE(SCS_BASE + 0x0010)
#define NVIC_BASE(SCS_BASE + 0x0100)
#define SCB_BASE(SCS_BASE + 0x0D00)

#ifdef _SCB
#define SCB((SCB_TypeDef *) SCB_BASE)
#endif

typedef struct
{
vu32 CPUID;
vu32 IRQControlState;
vu32 ExceptionTableOffset;
vu32 AIRC;
vu32 SysCtrl;
vu32 ConfigCtrl;
vu32 SystemPriority[3];
vu32 SysHandlerCtrl;
vu32 ConfigFaultStatus;
vu32 HardFaultStatus;
vu32 DebugFaultStatus;
vu32 MemoryManageFaultAddr;
vu32 BusFaultAddr;
} SCB_TypeDef;

其實(shí)這里主要就是要弄清楚這個(gè)SCB是什么意思，因?yàn)檫@個(gè)結(jié)構(gòu)是映射到一個(gè)物理地址上的。像別的控制寄存器都是這么個(gè)玩法，莫非這也是個(gè)某類控制器。google一下，果然對于系統(tǒng)控制寄存器組【上篇文章有提到】STM32的固件庫中有如下定義：

typedef struct
{
vuc32 CPUID;
vu32 ICSR;
vu32 VTOR;
vu32 AIRCR;
vu32 SCR;
vu32 CCR;
vu32 SHPR[3];
vu32 SHCSR;
vu32 CFSR;
vu32 HFSR;
vu32 DFSR;
vu32 MMFAR;
vu32 BFAR;
vu32 AFSR;
} SCB_TypeDef;

它們對應(yīng)ARM手冊中的名稱為
CPUID = CPUID Base Register
ICSR = Interrupt Control State Register
VTOR = Vector Table Offset Register
AIRCR = Application Interrupt/Reset Control Register
SCR = System Control Register
CCR = Configuration Control Register
SHPR = System Handlers Priority Register
SHCSR = System Handler Control and State Register
CFSR = Configurable Fault Status Registers
HFSR = Hard Fault Status Register
DFSR = Debug Fault Status Register
MMFAR = Mem Manage Address Register
BFAR = Bus Fault Address Register
AFSR = Auxiliary Fault Status Register

至此，我們終于清楚了，這個(gè)中斷向量表的地址，最終是要寫到某個(gè)控制器中去。那這么說來，上述的0x08000000可以是個(gè)別的值了，只要保證這一處的地址不能被別的程序訪問就行了。