異步與同步清零Verilog hdl表達程序

帶異步清0、異步置1 的D 觸發(fā)器
module DFF1(q,qn,d,clk,set,reset);
input d,clk,set,reset;
output q,qn;
reg q,qn;
always @(posedge clk or negedge set or negedge reset)
begin
if (!reset) begin
q <= 0; //異步清0，低電平有效
qn <= 1;
end
else if (!set) begin
q <= 1; //異步置1，低電平有效
qn <= 0;
end
else begin
q <= d;
qn <= ~d;
end
end
endmodule

帶同步清0、同步置1 的D觸發(fā)器
module DFF2(q,qn,d,clk,set,reset);
input d,clk,set,reset;
output q,qn;
reg q,qn;
always @(posedge clk)
begin
if (reset) begin
q <= 0; qn <= 1; //同步清0，高電平有效
end
else if (set) begin
q <=1; qn <=0; //同步置1，高電平有效
end
else begin
q <= d; qn <= ~d;
end
end
endmodule

異步清零：
always@(posedge clk or negedge rst )
begin
if(!rst) out <= 0;
else
begin ·················································
end
end

同步清零：
always@(posedgeclk)
begin
if(!rst) out <= 0;
else
begin ·················································
end
end