PIC 、APIC(IOAPIC LAPIC)
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PIC全稱Programmable Interrupt Controller，通常是指Intel 8259A雙片級(jí)聯(lián)構(gòu)成的最多支持15個(gè)interrupts的中斷控制系統(tǒng)。APIC全稱Advanced Programmable Interrupt Controller，APIC是為了多核平臺(tái)而設(shè)計(jì)的。它由兩個(gè)部分組成IOAPIC和LAPIC，其中IOAPIC通常位于南橋中
2. PIC
基于Intel 80x86的PC使用兩片8259A級(jí)聯(lián)的方式組成了可以管理15級(jí)中斷向量的一個(gè)中斷系統(tǒng)，下圖是它的一個(gè)連接示意圖。兩片8259A，一片為Master，另一片為Slaver。其中Slaver的INT接到Master的IRQ2上。8259A有兩種工作模式分別為編程和操作模式。BIOS初始化的時(shí)候會(huì)先通過IO port對(duì)8259A進(jìn)行編程配置，在此之后8259A就可以響應(yīng)來自外部設(shè)備的中斷請(qǐng)求了。Master的IO address是0x20 0x21; Slaver的IO address是0xA0 0xA1。
為了能夠正常的使用PIC來管理系統(tǒng)中斷，就需要對(duì)它進(jìn)行初始化。8259A支持兩種類型的命令字，一類是初始化命令字ICW1~4,另一類是操作命令字OCW1~3,其中每一個(gè)命令字的各個(gè)bit都有其代表的特定意義。下述是一個(gè)初始化Master的一個(gè)sample code：
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
3. APIC
Intel APIC由一組中斷輸入信號(hào)，一個(gè)24*64bit的Programmable Redirection Table(PRT)，一組register和用于從APIC BUS(FSB/QPI)上傳送APIC MSG的部件組成,當(dāng)南橋的IO device通過IOAPIC的interrupt lines產(chǎn)生interrupt，IOAPIC將根據(jù)內(nèi)部的PRT table格式化成中斷請(qǐng)求信息，并將該信息發(fā)送給目標(biāo)CPU的LAPIC，再由LAPIC通知CPU進(jìn)行處理。下圖是一個(gè)基于Intel APIC的連接示意圖，如下圖所示IOAPIC上有24個(gè)interrupt pin，每一個(gè)pin都對(duì)應(yīng)一個(gè)RTE,所以針對(duì)每一個(gè)interrupt pin都可以單獨(dú)設(shè)定它的mask，觸發(fā)方式(level,edge trigger),中斷管腳的極性，傳送方式，傳送狀態(tài)，目的地，中斷向量等。
Programmable Redirection Table詳細(xì)格式如下所示：
Bit Description: |
[63:56] Destination Field—R/W. |
[59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical destination address. Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID 1, Logical Mode IOREDTBLx[63:56] = Set of processors |
[55:17] Reserved.82093AA (IOAPIC) |
[16] interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. It is softwares responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. When this bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination. |
[15] Trigger Mode—R/W. |
[14] Remote IRR—RO. |
[13] Interrupt Input Pin Polarity (INTPOL)—R/W. signal. 0=High active, 1=Low active. |
[12] delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time). |
[11] Destination Mode (DESTMOD)—R/W. Destination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID. Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC. Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC) |
[10:8]Delivery Mode (DELMOD)—R/W. Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode. These restrictions are indicated in the following table for each Delivery Mode. Mode Description 000 destination. Trigger Mode for "fixed" Delivery Mode can be edge or level. 001 Priority Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode for "lowest priority". Delivery Mode can be edge or level. 010 edge trigger mode. The vector information is ignored but must be programmed to all zeroes for future compatibility. 011 100 destination. Vector information is ignored. NMI is treated as an edge triggered interrupt, even if it is programmed as a level triggered interrupt. For proper operation, this redirection table entry must be programmed to “edge” triggered interrupt. 101 asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt, even if programmed otherwise. For proper operation, this redirection table entry must be programmed to “edge” triggered interrupt. 110 111 destination as an interrupt that originated in an externally connected (8259A-compatible) interrupt controller. The INTA cycle that corresponds to this ExtINT delivery is routed to the external controller that is expected to supply the vector. A Delivery Mode of "ExtINT" trigger mode. |
[7:0] Interrupt Vector (INTVEC)—R/W: vector for this interrupt. Vector values range from 10h to FEh. |
REFF:
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That’s all!
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