電腦鍵盤工作原理
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總線空閑時(shí)，兩條線都是高電平(集電極開路)。
This is the only state where the keyboard/mouse is allowed begin transmitting data.
在這種狀態(tài)下，鍵盤/鼠標(biāo)才允許開始傳輸數(shù)據(jù)。
The host has ultimate control over the bus and may inhibit communication at any time by pulling the Clock line low.
主機(jī)對(duì)總線有最高的控制權(quán)，在任何時(shí)候通過將時(shí)鐘線拉低就可以禁止通信。
The device always generates the clock signal.
時(shí)鐘信號(hào)總是由設(shè)備端生成的。
If the host wants to send data, it must first inhibit communication from the device by pulling Clock low.
如果主機(jī)想發(fā)送數(shù)據(jù)，它必須先將時(shí)鐘拉低來禁止來自設(shè)備端的通信。
The host then pulls Data low and releases Clock.
然后主機(jī)再拉低數(shù)據(jù)線，釋放時(shí)鐘。 注釋:釋放時(shí)鐘，就是再恢復(fù)時(shí)鐘為高
This is the "Request-to-Send" state and signals the device to start generating clock pulses.
這就是"請(qǐng)求發(fā)送(Request-to-Send)"狀態(tài)，提示 設(shè)備端 開始生成時(shí)鐘信號(hào)。
Summary: Bus States
Data = high, Clock = high: Idle state.
Data = high, Clock = low: Communication Inhibited.
Data = low, Clock = high: Host Request-to-Send
總結(jié):總線狀態(tài)
數(shù)據(jù) 0 1
0 ---------通信禁止-----------
時(shí)鐘
1 主機(jī)要求發(fā)送 總線空閑
The clock and data pins are bidirectional, open-collector
signals that are pulled to 5 V by pullup resistors in the keyboard.
時(shí)鐘和數(shù)據(jù) 引腳時(shí) 雙向 集電極開路的信號(hào)，可以被鍵盤內(nèi)部的上拉電阻 拉高到5V
Data sent from the device to the host is read on the falling edge of the clock signal; data sent from the host to the device is read on the rising edge.
從設(shè)備發(fā)送給主機(jī)的數(shù)據(jù)時(shí)在時(shí)鐘信號(hào)的下降沿讀取的;從主機(jī)發(fā)給設(shè)備的數(shù)據(jù)是在上升沿讀取的。
The clock frequency must be in the range 10 - 16.7 kHz. This means clock must be high for 30 - 50 microseconds and low for 30 - 50 microseconds..
時(shí)鐘頻率必須在10-16.7KHz之間。這意味著時(shí)鐘必須是 高電平持續(xù)30～50毫秒，低電平持續(xù)
30～50毫秒。
If you're designing a keyboard, mouse, or host emulator, you should modify/sample the Data line in the middle of each cell. I.e. 15 - 25 microseconds after the appropriate clock transition.
如果你設(shè)計(jì)一個(gè)鍵盤 鼠標(biāo) 或者 主機(jī)模擬器，你必須 在每個(gè)單元的中間時(shí)刻 （也就是,在時(shí)鐘跳變之后的15～25毫秒后） 修改/取樣數(shù)據(jù)線.
Again, the keyboard/mouse always generates the clock signal, but the host always has ultimate control over communication.
重復(fù)一遍，鍵盤/鼠標(biāo) 總是 生成時(shí)鐘信號(hào)， 而 主機(jī) 控制著整個(gè)通信過程。
Timing is absolutely crucial. Every time quantity I give in this article must be followed exactly.
時(shí)序是非常重要的。在本文中給出的時(shí)間數(shù)必須嚴(yán)格遵循。
設(shè)備發(fā)送數(shù)據(jù)到主機(jī)
The Data and Clock lines are both open collector.
數(shù)據(jù)和時(shí)鐘線都是集電極開路的。
A resistor is connected between each line and +5V, so the idle state of the bus is high.
在+5V 和每根線 之間連接著一個(gè)電阻，所以 總線的空閑狀態(tài) 是 高電平。
When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a high logic level.
當(dāng)鍵盤或者鼠標(biāo)想發(fā)送數(shù)據(jù)時(shí)，它首先必須檢查時(shí)鐘線 ，確認(rèn)它處于高電平。
If it's not, the host is inhibiting communication and the device must buffer any to-be-sent data until the host releases Clock.
如果不是，主機(jī)禁止通信，設(shè)備必須緩沖任何要發(fā)送的數(shù)據(jù)，直到主機(jī)釋放時(shí)鐘。
The Clock line must be continuously high for at least 50 microseconds before the device can begin to transmit its data.
在設(shè)備開始傳輸數(shù)據(jù)之前，時(shí)鐘線 必須持續(xù)為 高電平的 時(shí)間 必須 至少50ms
The keyboard/mouse writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low.
當(dāng)時(shí)鐘為高電平時(shí)，鍵盤/鼠標(biāo)寫一個(gè)bit到數(shù)據(jù)線上；當(dāng)時(shí)鐘為低電平時(shí)，主機(jī)從數(shù)據(jù)線上讀取這個(gè)bit 。
The Data line changes state when Clock is high and that data is valid when Clock is low.
當(dāng)時(shí)鐘位高時(shí)，數(shù)據(jù)線 改變狀態(tài)；
當(dāng)時(shí)鐘位低時(shí)，（數(shù)據(jù)線上的)數(shù)據(jù)是有效的。
The clock frequency is 10-16.7 kHz.
時(shí)鐘頻率是10-16.7KHz
The time from the rising edge of a clock pulse to a Data transition must be at least 5 microseconds.
從時(shí)鐘脈沖的上升沿到數(shù)據(jù)跳變 的時(shí)間必須至少 5ms
The time from a data transition to the falling edge of a clock pulse must be at least 5 microseconds and no greater than 25 microseconds.
從數(shù)據(jù)跳變 到時(shí)鐘脈沖的下降沿 必須 至少5ms,且不超過25ms
The host may inhibit communication at any time by pulling the Clock line low for at least 100 microseconds.
主機(jī)可在任何時(shí)間禁止通信，只需要將時(shí)鐘線下拉位低電平超過100ms即可
If a transmission is inhibited before the 11th clock pulse, the device must abort the current transmission and prepare to retransmit the current "chunk" of data when host releases Clock.
如果在第11個(gè)脈沖時(shí)禁止傳輸，設(shè)備必須中止當(dāng)前的傳輸，準(zhǔn)備重新傳輸當(dāng)前的數(shù)據(jù)"chunk（塊)"當(dāng)主機(jī)釋放時(shí)鐘時(shí)
A "chunk" of data could be a make code, break code, device ID, mouse movement packet, etc.
一個(gè)數(shù)據(jù)塊可能時(shí) 通碼，斷碼，設(shè)備ID，鼠標(biāo)移動(dòng)包 等等。
For example, if a keyboard is interrupted while sending the second byte of a two-byte break code, it will need to retransmit both bytes of that break code, not just the one that was interrupted.
舉個(gè)例子，如果當(dāng)發(fā)送 一個(gè)兩字節(jié)斷碼的 第2個(gè)字節(jié)時(shí)，鍵盤被中斷，它將需要重新發(fā)送
此斷碼的兩個(gè)字節(jié)，而不僅僅時(shí)被中斷掉的那個(gè)字節(jié)。
If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data.
如果在第一個(gè) 高->低 時(shí)鐘跳變 時(shí)，（或者在 最后一個(gè)時(shí)鐘脈沖的下降沿 之后）主機(jī)將時(shí)鐘拉低，鍵盤/鼠標(biāo) 不必重新傳輸任何數(shù)據(jù)。
However, if new data is created that needs to be transmitted, it will have to be buffered until the host releases Clock.
但是，如果新產(chǎn)生的數(shù)據(jù)需要傳輸，它必須將數(shù)據(jù)緩沖，知道主機(jī)釋放時(shí)鐘。
Keyboards have a 16-byte buffer for this purpose. If more than 16 bytes worth of keystrokes occur, further keystrokes will be ignored until there's room in the buffer.
鍵盤有一個(gè)16字節(jié)的緩沖區(qū)。如果有超過16個(gè)字節(jié)的擊鍵存在，更多的擊鍵將被忽略。直到
緩沖區(qū)有空地。
Mice only store the most current movement packet for transmission.
鼠標(biāo)只能緩沖最近的一個(gè)要傳輸?shù)模ㄒ苿?dòng))數(shù)據(jù)包。
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Time to auxiliary device inhibit after clock 11 to ensure the auxiliary device does not start another transmission
The auxiliary device checks the 'clock' l
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