Design Challenges for an Ultra
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Figure 6. Simulation test results using a VC phase noise was at 4GHz.
With the PFD noise removed, the filter is set close to optimal for the VCO noise peak at 10kHz. The major remaining problem is reference noise, and unfortunately, the better-than-mask performance beyond 40kHz is not enough to offset this noise. So the possibility remains that another oscillator, perhaps an OCXO, must be used to meet the phase-noise requirements.
The printed circuit board (PCB) for this design will include pads for three or four different XO footprints. Figure 7 shows the simulation results using the Vectron OCXO. Even with the PFD noise included, the resulting jitter is about 86.5fs. This jitter value offers some headroom both for the yet unaccounted for divider phase noise (which should have almost no impact) and for the amplifier stage that is probably needed.
Figure 7. Simulation results with the Vectron OXCO; phase noise was at 4GHz.
Conclusion
The 100fs jitter target at 2GHz proved harder to attain than originally anticipated. Data indicate that it can be achieved using a fairly standard PLL circuit. The key design components are the VCO and the reference oscillator. UMX proved to have VCOs with best-in-class phase-noise performance. The remaining two hurdles are: (1) selecting a reference oscillator with sufficiently low noise; and (2) selecting an appropriate gain amplifier. Fortunately, there are many sources of these components, so a good strategy will plan the initial layout to include several different popular footprints. The gain amplifier is more difficult; further analysis will determine whether it can be placed within the loop and what noise impact it will have.
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