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DS26303 LIU的初始化和配置

——

作者：時(shí)間：2007-01-26 來源：《Maxim》

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引言

　　在為一個(gè)新設(shè)計(jì)的電信系統(tǒng)開發(fā)軟件時(shí)，最棘手的任務(wù)莫過于實(shí)現(xiàn)基本的設(shè)備操作。DS26303收發(fā)器的大量功能和多端口操作使軟件開發(fā)更趨復(fù)雜。為了方便初期系統(tǒng)開發(fā)，Dallas Semiconductor公司提供了C風(fēng)格范例代碼，它可以在T1或E1模式下初始化設(shè)備，軟件開發(fā)人員只需針對所需的操作修改代碼，或編寫與特定系統(tǒng)相關(guān)的功能。一旦代碼編譯完畢，即可載入系統(tǒng)進(jìn)行測試與評估。需要注意的是DS26303有兩個(gè)版本，分別是DS26303-120和DS26303-75。它們的區(qū)別很小，只會影響到幾個(gè)設(shè)置，因此需要弄清楚設(shè)計(jì)中用到的是哪個(gè)器件。

代碼范例

　　圖1中所示的范例代碼在稍加修改之后就可以正確編譯以供目標(biāo)系統(tǒng)使用。write(address,data)和wait(milliseconds)兩個(gè)函數(shù)調(diào)用過程與系統(tǒng)相關(guān)，因此需要根據(jù)所用的微處理器編寫。該代碼假定設(shè)備被映射到16位的本地總線(地址偏移0x0000)，并且設(shè)備的數(shù)據(jù)總線為8位。對于其他情況，則需要修改代碼或編寫函數(shù)調(diào)用來解決。此段代碼還包含某些寄存器的多種不同設(shè)置，從而為開發(fā)人員提供了時(shí)鐘頻率、線路編碼等參數(shù)的多種選擇。雖然包含了大量的基本功能，但該代碼并不完備。當(dāng)需要實(shí)現(xiàn)其他附加功能時(shí)，請參考數(shù)據(jù)資料。

/*
Configuration Example For DS26303-120 running in E1 mode.

This Example assumes E1 operation so the function call for T1/J1 configuration
has been commented out. Simply comment out the E1 configuration function
call and uncomment the T1 configuration function call for T1 operation. An
individual function call for J1 operation is not present because it is very
similar to T1 operation and could easily be implemented in that function.

This file follows C style conventions. However actual code for the function
calls listed below are implementation specific and need to be added:

Function Calls: write(address, data), wait(milliseconds)

The following comments only indicate some of the possible clock sources
that can be used for either E1 or T1/J1 operation.

Master clock configuration can use multiples of n = 1, 2, 4, or 8
MCLK = Can be a n x 1.544 or n x 2.048 MHz signal for E1 or T1/J1 Operation

TCLK = Must be a 2.048 MHz Signal for E1 Operation
TCLK = Must be a 1.544 MHz signal for T1/J1 Operation
*/

void initialization_main()
{
/* Global Initialization Begin */

/* Reset all channels to their default values */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
Write(0x000A, 0xFF); // SWR, Reset All Channels

/* Wait 1 ms for reset to complete */
wait (1);

/* The Master Clock Select Register is important for proper */
/* device operation consult the data sheet for all possible configurations. */
write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual LIU Register Bank
write(0x0006, 0x00); // MC, E1 Mode Only MCLK-2.048, TECLK & CLKA Disabled
// write(0x0006, 0x00); // MC, T1/J1 Mode Only MCLK-1.544, TECLK & CLKA Disabled

// write(0x0006, 0x03); // MC, T1/J1 or E1 Mode MCLK-1.544, TECLK & CLKA Disabled
// write(0x0006, 0x07); // MC, T1/J1 or E1 Mode MCLK-3.088, TECLK & CLKA Disabled
// write(0x0006, 0x0B); // MC, T1/J1 or E1 Mode MCLK-6.176, TECLK & CLKA Disabled
// write(0x0006, 0x0F); // MC, T1/J1 or E1 Mode MCLK-12.352, TECLK & CLKA Disabled

// write(0x0006, 0x01); // MC, T1/J1 or E1 Mode MCLK-2.048, TECLK & CLKA Disabled
// write(0x0006, 0x05); // MC, T1/J1 or E1 Mode MCLK-4.096, TECLK & CLKA Disabled
// write(0x0006, 0x09); // MC, T1/J1 or E1 Mode MCLK-8.192, TECLK & CLKA Disabled
// write(0x0006, 0x0D); // MC, T1/J1 or E1 Mode MCLK-16.384, TECLK & CLKA Disabled

/* Wait 1 ms for clock to settle after configuration */
wait (1);

/* The GC register is able to globally control the AIS During LOS, Short Circuit */
/* Protection, Line Coding, JA Depth, JA Position, and JA Enable functions */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x000F, 0x80); // GC, Enable RX Internal Impedance, Disable Global Controls

/* Global Initialization Complete */

/* Configuration Begin */

e1_configure();

// t1_configure();

/* Configuration Complete */
}{{分頁}}

void e1_configure()
{
/* E1 Initilization Begin */

/* This function assumes all ports are configured identically. Otherwise, */
/* the function needs to be revised to support individual port addressing */
/* and identification. */

/* Configure analog, remote, or digital loopback as necessary */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x0001, 0x00); // ALBC, Disable Analog Loopback for 8 Channels
// write(0x0001, 0xFF); // ALBC, Enable Analog Loopback for 8 Channels
write(0x0002, 0x00); // RLBC, Disable Remote Loopback for 8 Channels
// write(0x0002, 0xFF); // RLBC, Enable Remote Loopback for 8 Channels
write(0x000C, 0x00); // DLBC, Disable Digital Loopback for 8 Channels
// write(0x000C, 0xFF); // DLBC, Enable Digital Loopback for 8 Channels

/* Configure LOS / AIS criteria in E1 mode */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x000D, 0x00); // LASCS, Use G.775 Criteria for 8 Channels
// write(0x000D, 0xFF); // LASCS, Use ETSI 300233 Criteria for 8 Channels

write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x0003, 0x00); // TAOE, Disable Transmit All Ones for 8 Channels
// write(0x0003, 0xFF); // TAOE, Enable Transmit All Ones for 8 Channels

write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x000E, 0x00); // ATAOS, Disable Automatic Transmit All Ones for 8 Channels
// write(0x000E, 0xFF); // ATAOS, Enable Automatic Transmit All Ones for 8 Channels

write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x0012, 0x00); // OEB, Disable TX Output High Impedance for 8 Channels
// write(0x0012, 0xFF); // OEB, Enable TX Output High Impedance for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0003, 0x00); // RPDE, Disable Receive Power-Down for 8 Channels
// write(0x0003, 0xFF); // RPDE, Enable Receive Power-Down for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0004, 0x00); // TPDE, Disable Transmit Power-Down for 8 Channels
// write(0x0004, 0xFF); // TPDE, Enable Transmit Power-Down for 8 Channels

/* In single rail mode (SMRS register) with HDB3/B8ZS (LCS register) enabled, */
/* the EZDE and CVDEB registers can enable the excessive zero and code */
/* violation detection output on the RNEG pin. */
write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
// write(0x0000, 0x00); // SRMS, Disable Single Rail Mode I/O for 8 Channels
write(0x0000, 0xFF); // SRMS, Enable Single Rail Mode I/O for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0005, 0x00); // EZDE, Disable Excessive Zero Detect for 8 Channels
// write(0x0005, 0xFF); // EZDE, Enable Excessive Zero Detect for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0006, 0x00); // CVDEB, Enable Code Violation Detect for 8 Channels
// write(0x0006, 0xFF); // CVDEB, Disable Code Violation Detect for 8 Channels

/* The following six functions can be controlled individually on a per channel */
/* basis or globally using the GC register. The IAISEL, ISCPD, LCS, IJAFDS, */
/* IJAPS, and IJAE are ignored when the corresponding function in the GC */
/* register is enabled. */
write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
write(0x0005, 0x00); // IAISEL, Disable Indiv AIS During LOS for 8 Channels
// write(0x0005, 0xFF); // IAISEL, Enable Indiv AIS During LOS for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
write(0x0004, 0x00); // ISCPD, Enable Indiv Short Protection for 8 Channels
// write(0x0004, 0xFF); // ISCPD, Disable Indiv Short Protection for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0001, 0x00); // LCS, Enable B8ZS/HDB3 Operation for 8 Channels
// write(0x0001, 0xFF); // LCS, Enable AMI Operation for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
// write(0x0002, 0x00); // IJAFDS, Indiv JA 32 Bit Depth for 8 Channels
write(0x0002, 0xFF); // IJAFDS, Indiv JA 128 Bit Depth for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
// write(0x0001, 0x00); // IJAPS, Indiv JA Transmit Path for 8 Channels
write(0x0001, 0xFF); // IJAPS, Indiv JA Receive Path for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
// write(0x0000, 0x00); // IJAE, Disable Indiv Jitter Attenuator for 8 Channels
write(0x0000, 0xFF); // IJAE, Enable Indiv Jitter Attenuator for 8 Channels

/* Configure all channels for a E1 pulse template output. This example uses */
/* the DS26303-120 device so, TS.TIMPRM = 0 for 120 ohm line impedances. If */
/* the device were a DS26303-75, TS.TIMPRM = 1 for 120 ohm line impedances. */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank

Write(0x0010, 0x00) // TST, Select Channel 1 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x01) // TST, Select Channel 2 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x02) // TST, Select Channel 3 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x03) // TST, Select Channel 4 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x04) // TST, Select Channel 5 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x05) // TST, Select Channel 6 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x06) // TST, Select Channel 7 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match

Write(0x0010, 0x07) // TST, Select Channel 8 for Template Configuration
Write(0x0011, 0x00) // TS, E1 Mode 120 ohm G.703 TX/RX Impedance Match
}{{分頁}}

void t1_configure()
{
/* T1 Initilization Begin */

/* This function assumes all ports are configured identically. Otherwise, */
/* the function needs to be revised to support individual port addressing */
/* and identification. */

/* Configure analog, remote, or digital loopback as necessary */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x0001, 0x00); // ALBC, Disable Analog Loopback for 8 Channels
// write(0x0001, 0xFF); // ALBC, Enable Analog Loopback for 8 Channels
write(0x0002, 0x00); // RLBC, Disable Remote Loopback for 8 Channels
// write(0x0002, 0xFF); // RLBC, Enable Remote Loopback for 8 Channels
write(0x000C, 0x00); // DLBC, Disable Digital Loopback for 8 Channels
// write(0x000C, 0xFF); // DLBC, Enable Digital Loopback for 8 Channels

write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x0003, 0x00); // TAOE, Disable Transmit All Ones for 8 Channels
// write(0x0003, 0xFF); // TAOE, Enable Transmit All Ones for 8 Channels

write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x000E, 0x00); // ATAOS, Disable Automatic Transmit All Ones for 8 Channels
// write(0x000E, 0xFF); // ATAOS, Enable Automatic Transmit All Ones for 8 Channels

write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank
write(0x0012, 0x00); // OEB, Disable TX Output High Impedance for 8 Channels
// write(0x0012, 0xFF); // OEB, Enable TX Output High Impedance for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0003, 0x00); // RPDE, Disable Receive Power-Down for 8 Channels
// write(0x0003, 0xFF); // RPDE, Enable Receive Power-Down for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0004, 0x00); // TPDE, Disable Transmit Power-Down for 8 Channels
// write(0x0004, 0xFF); // TPDE, Enable Transmit Power-Down for 8 Channels

/* In single rail mode (SMRS register) with HDB3/B8ZS (LCS register) enabled, */
/* the EZDE and CVDEB registers can enable the excessive zero and code */
/* violation detection output on the RNEG pin. */
write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
// write(0x0000, 0x00); // SRMS, Disable Single Rail Mode I/O for 8 Channels
write(0x0000, 0xFF); // SRMS, Enable Single Rail Mode I/O for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0005, 0x00); // EZDE, Disable Excessive Zero Detect for 8 Channels
// write(0x0005, 0xFF); // EZDE, Enable Excessive Zero Detect for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0006, 0x00); // CVDEB, Enable Code Violation Detect for 8 Channels
// write(0x0006, 0xFF); // CVDEB, Disable Code Violation Detect for 8 Channels

/* The following six functions can be controlled individually on a per channel */
/* basis or globally using the GC register. The IAISEL, ISCPD, LCS, IJAFDS, */
/* IJAPS, and IJAE are ignored when the corresponding function in the GC */
/* register is enabled. */
write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
write(0x0005, 0x00); // IAISEL, Disable Indiv AIS During LOS for 8 Channels
// write(0x0005, 0xFF); // IAISEL, Enable Indiv AIS During LOS for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
write(0x0004, 0x00); // ISCPD, Enable Indiv Short Protection for 8 Channels
// write(0x0004, 0xFF); // ISCPD, Disable Indiv Short Protection for 8 Channels

write(0x001F, 0xAA); // ADDP, Set Address Pointer to Secondary Register Bank
write(0x0001, 0x00); // LCS, Enable B8ZS/HDB3 Operation for 8 Channels
// write(0x0001, 0xFF); // LCS, Enable AMI Operation for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
// write(0x0002, 0x00); // IJAFDS, Indiv JA 32 Bit Depth for 8 Channels
write(0x0002, 0xFF); // IJAFDS, Indiv JA 128 Bit Depth for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
// write(0x0001, 0x00); // IJAPS, Indiv JA Transmit Path for 8 Channels
write(0x0001, 0xFF); // IJAPS, Indiv JA Receive Path for 8 Channels

write(0x001F, 0x01); // ADDP, Set Address Pointer to Individual Register Bank
// write(0x0000, 0x00); // IJAE, Disable Indiv Jitter Attenuator for 8 Channels
write(0x0000, 0xFF); // IJAE, Enable Indiv Jitter Attenuator for 8 Channels

/* Configure all channels for a T1 pulse template output */
write(0x001F, 0x00); // ADDP, Set Address Pointer to Primary Register Bank

Write(0x0010, 0x00) // TST, Select Channel 1 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x01) // TST, Select Channel 2 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x02) // TST, Select Channel 3 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x03) // TST, Select Channel 4 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x04) // TST, Select Channel 5 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x05) // TST, Select Channel 6 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x06) // TST, Select Channel 7 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

Write(0x0010, 0x07) // TST, Select Channel 8 for Template Configuration
Write(0x0011, 0x07) // TS, T1 Mode 100 ohm 533-655 ft. TX/RX Impedance Match

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