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          EEPW首頁(yè) > 嵌入式系統(tǒng) > 設(shè)計(jì)應(yīng)用 > 用EEPROM對(duì)大容量FPGA芯片數(shù)據(jù)實(shí)現(xiàn)串行加載

          用EEPROM對(duì)大容量FPGA芯片數(shù)據(jù)實(shí)現(xiàn)串行加載

          作者: 時(shí)間:2010-03-03 來(lái)源:網(wǎng)絡(luò) 收藏

            雖然該程序是針對(duì)XCV100芯片及AT29C010A 設(shè)計(jì)的,但對(duì)于其他芯片同樣適用,不同的是針對(duì)不同容量的,應(yīng)改變其地址計(jì)數(shù)器的位數(shù)。

            Library IEEE;
          Use IEEE.Std_logic_1164.a(chǎn)ll;
          Use ieee.Std_logic_arith.all;
          Use ieee.Std_logic_unsigned.all;
          Entity v10sload is
          port 
          pDATA in STD_LOGIC_VECTOR 7 downto 0 
          Paddress inout STD_LOGIC_VECTOR 16
          Downto 0 
          CCLKIN in STD_LOGIC
          RESET in STD_LOGIC
          DATAINo(wú)ut STD_LOGIC
           
          end v10sload

            architecture v10sload_arch of v10sload is
          signal loadin CE Nce CCLK8 Nreset nCCLK aDATAIN
          bDATAIN std_logic
          signal clkenable CCLK std_logic
          signal ppDATA std_logic_vector 7 downto 0 
          component clk_div8
          PORT
          CLOCKASYNC_CTRL IN std_logic
          CLK_OUT OUT std_logic 
          end component
          component R_shift8
          PORT
          D_IN IN std_logic_vector 7 DOWNTO 0 
          LOAD IN std_logic
          CLK_EN IN std_logic
          CLOCK IN std_logic
          LS_OUT OUT std_logic 
          end component
          component BUFG
          port I in std_logic O out std_logic 
          end component
          begin
          -------------------------------
          --data-loading function statements here
          nRESET<=not RESET
          init_dataprocessRESET 
          begin
          if RESET='0'  then
          ppDATA<=″00000000″
          else ppDATA<=pDATA
          end if
          end process init_data
          L0 BUFG port mapI=>CCLKIN O=>CCLK 
          nCCLK<=not CCLK
          L1counter17 portmap
          CLOCK=>CCLK8ASYNC_CTRL=>nRESET
          Q_OUT=>pADDRESS 
          L2 clk_div8 portmap
          CLOCK=>nCCLKASYNC_CTRL=>nRESET
          CLK_OUT=>CCLK8 
          nCE<=not pADDRESS0 
          CE<=pADDRESS0 
          clkenable<='1'
          L3R_shift8 portmap
          D_IN=>ppDATALOAD=>nCECLK_EN=>
          clkenableCLOCK=>nCCLK
          LS_OUT=>aDATAIN 
          L4R_shift8 portmap
          D_IN=>ppDATALOAD=>CECLK_EN=>
          clkenableCLOCK=>nCCLK
          LS_OUT=>bDATAIN 
          Process Adatain bDATAIN CE 
          begin
          if CE='1'  then DATAIN<=dDATAIN
          else DATAIN<=bDATAIN
          end if
          end process
          end v10sload_arch

            參考文獻(xiàn)

            1 XILINX 公司DATABOOK,199954~56

            2 XILINX公司網(wǎng)站www.xilinx.com

            3 王小軍.VHDL 簡(jiǎn)明教程.北京:清華大學(xué)出版社,1997


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