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class="tvvx9jz" id="container"> <section> <article> <h1>轉(zhuǎn)變硬件成軟件：多核心環(huán)境的高效程序?qū)懽?/h1> <div id="7dfh9dn" class="subhead" style="padding-bottom:15px;padding-right:50px;font-size:16px;color:#252525;font-style:normal;text-align:center;">—— </div> <div id="pzffpfh" class="authorTimeSource"> <span>作者：Skip Hovsmith CriticalBlue</span> <span>時(shí)間：2007-12-28</span> <span>來源：ARM IQ雜志</span> <link rel="stylesheet" type="text/css"/> <span style="float:right; width:130px;margin-right:0px; text-align:right;"> <div id="ppxvnvd" class="nav0"> <ul> <li><a href="javascript:void(0);"><img src="http://www.ex-cimer.com/event/action/images/icon_add_4.png" width="20" border="0" align="absmiddle" />加入技術(shù)交流群</a> <ul> <li style="text-align:center;"><img src="http://www.ex-cimer.com/event/company/images/code_1.jpg" width="130"><br />掃碼加入<br />和技術(shù)大咖面對面交流<br />海量資料庫查詢</li> </ul> </li> </ul> </div> </span> <span style="float:right; width:30px;margin-right:0px; text-align:right;"><a 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透過自動(dòng)化的處理器同步，我們能降低研發(fā)特殊應(yīng)用協(xié)同處理器所需的成本與時(shí)間，并透過以<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/軟件"><em>軟件</em></a>為中心的模式來開發(fā)產(chǎn)品。 <BR><BR> <a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/軟件"><em>軟件</em></a>的功能性建立之后，關(guān)鍵的<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/軟件"><em>軟件</em></a>工作可分擔(dān)給已針對該應(yīng)用進(jìn)行過最佳化的協(xié)同處理器來執(zhí)行。每個(gè)協(xié)同處理器都已針對效能、即時(shí)、以及空間等方面的要求進(jìn)行最佳化設(shè)計(jì)，并且完全可<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/程序"><em>程序</em></a>化，因此在上市后還能進(jìn)行擴(kuò)充與優(yōu)化功能的動(dòng)作。協(xié)同處理器的簡化與速度可以提供更大的機(jī)板設(shè)計(jì)空間，相同的軟件也可重新設(shè)定不同的目標(biāo)以因應(yīng)不同的產(chǎn)品價(jià)位與效能需求。 <BR><BR> 業(yè)者必須運(yùn)用多核心架構(gòu)來因應(yīng)<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/嵌入式"><em>嵌入式</em></a>電子系統(tǒng)對于高效能與低功耗的需求。根據(jù)International Business Strategies（IBS）的研究顯示，<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/嵌入式"><em>嵌入式</em></a>軟件在90納米領(lǐng)域已成為一項(xiàng)主流設(shè)計(jì)模式。<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/嵌入式"><em>嵌入式</em></a>軟件如今主導(dǎo)SoC設(shè)計(jì)。 <BR><BR> IBS的這項(xiàng)研究也發(fā)現(xiàn)，架構(gòu)設(shè)計(jì)的工作投入現(xiàn)在出現(xiàn)大幅增加的趨勢。而大多數(shù)的投入是為了提升處理與通訊的效率，以確保能達(dá)成嵌入式軟件的效能目標(biāo)。即使針對開發(fā)架構(gòu)的投入越來越多，<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/硬件"><em>硬件</em></a>設(shè)計(jì)的昂貴成本仍然限制業(yè)者進(jìn)行擴(kuò)大架構(gòu)開發(fā)的意愿。 <BR><BR> 隨著處理器同步技術(shù)的進(jìn)步，開發(fā)特定應(yīng)用處理組件的時(shí)間與成本已被大幅降低，并創(chuàng)造出以軟件為中心的開發(fā)模式。業(yè)者現(xiàn)在可以直接掌控更高比率的軟件研發(fā)工作，也可針對實(shí)際軟件的處理負(fù)荷進(jìn)行架構(gòu)最佳化的調(diào)整。特定應(yīng)用處理器可進(jìn)行同步以滿足各種功能系統(tǒng)的效能需求，并讓系統(tǒng)擁有最高的可<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/程序"><em>程序</em></a>化彈性。如此一來，更多<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/硬件"><em>硬件</em></a>組件將可轉(zhuǎn)化成軟件，而不是背道而馳。 <BR><BR> 分布式協(xié)同處理 <BR><BR> 大多數(shù)<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/嵌入式系統(tǒng)"><em>嵌入式系統(tǒng)</em></a>工程師都熟悉單處理器的編程模式。但多個(gè)獨(dú)立運(yùn)作的核心讓這種編程模式變得更加復(fù)雜。為維持較簡單的編程模式，可把一個(gè)或多個(gè)處理組件指派為全域的主控制器，而其它核心則視為協(xié)同處理組件，如圖一所示。 <BR><BR> 在一個(gè)異質(zhì)化架構(gòu)中，系統(tǒng)功能被分散至各個(gè)協(xié)同處理組件以降低這些組件的耦合性。松散的耦合模式增加了平行處理的機(jī)率，但各組件的運(yùn)算負(fù)荷卻各有所異。每一個(gè)處理組件皆可進(jìn)行最佳化來配合其處理需求。 <BR><BR> <IMG src="/news/upload/20071228100414654.jpg" border=0><BR><BR> 圖一：分布式協(xié)同處理架構(gòu)。 <BR><BR> 替代的協(xié)同處理組件包括從數(shù)碼訊號處理器（DSP），ㄧ直到固定功能的<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/硬件"><em>硬件</em></a>加速器等各種可<a class="contentlabel" href="http://www.ex-cimer.com/news/listbylabel/label/程序"><em>程序</em></a>化的核心。 <BR><BR> 應(yīng)用協(xié)同處理器是一種為特定應(yīng)用設(shè)計(jì)微架構(gòu)以快速執(zhí)行關(guān)鍵算法的可程序化處理器。這些客制化處理器具備最大化的編程效能，同時(shí)讓處理作業(yè)在內(nèi)部就能完成以維持較簡單的編程模式。但客制化處理器昂貴的設(shè)計(jì)與驗(yàn)證成本，讓這種模式的推廣面臨極大的阻力。不過如今業(yè)界出現(xiàn)各種自動(dòng)化協(xié)同處理器合成工具，讓這種模式的吸引力持續(xù)攀升。 <BR><BR> 應(yīng)用協(xié)同處理器同步 <BR><BR> 處理器同步工具必須針對應(yīng)用作業(yè)的需求，來開發(fā)出處理器的實(shí)作方案。如圖二所示，串疊式的協(xié)同處理器同步流程采用一種修改后的VLIW模式。如同客制化的硬件設(shè)計(jì)，暫存器分布在各執(zhí)行單元并以客制化的連結(jié)管道來連結(jié)關(guān)鍵應(yīng)用所需的資料流。而資料與指令快取是用來降低對外部存儲(chǔ)器的需求，圖二的范例顯示了兩個(gè)資料快取。由于協(xié)同處理器是針對特定應(yīng)用所設(shè)計(jì)，因此合理的作法是運(yùn)用多個(gè)資料快取，并依據(jù)算法的資料需求來策略性配置每個(gè)快取的容量。選擇合適的指令編碼模式，可以增進(jìn)平行處理的效率并降低微碼（microcode）的長度。 <BR><BR> <IMG src="/news/upload/20071228100447262.jpg" border=0><BR><BR> 圖二：協(xié)同處理器架構(gòu)。 <BR><BR> 一個(gè)或多個(gè)協(xié)同處理器可從應(yīng)用程序進(jìn)行同步，圖三顯示單一協(xié)同處理器的同步流程。 <BR><BR> 同步的進(jìn)入點(diǎn)是編譯過的二進(jìn)工藝序碼，軟件開發(fā)人員運(yùn)用其正常的主處理器工具鏈來編譯其程序碼。我們可用對應(yīng)（profiling）與其它的效能分析工具來找出功能效能的關(guān)鍵點(diǎn)。在發(fā)現(xiàn)之后，這些功能將可轉(zhuǎn)移給特定應(yīng)用處理器來執(zhí)行。 <BR><BR> <IMG src="/news/upload/20071228100509444.jpg" border=0><BR><BR> 圖三：協(xié)同處理器合成流程。 <BR><BR> 從可執(zhí)行的二進(jìn)工藝序開始，任何編譯語言以及其編譯的程序都可進(jìn)行加速。包括C語言以及經(jīng)過最佳化的組譯語言，而此階段不需要原始碼。 <BR><BR> 二進(jìn)工藝序碼讀入系統(tǒng)后，便可選擇要分擔(dān)至協(xié)同處理器的功能。此時(shí)要建立二進(jìn)工藝序碼的模型并進(jìn)行模擬，詳細(xì)追蹤存儲(chǔ)器的使用模式以及關(guān)鍵的執(zhí)行線路。追蹤信息是用來分析不同的資料快取、執(zhí)行單元以及聯(lián)結(jié)的組合。產(chǎn)生各種不同效能、空間與耗電量組態(tài)的協(xié)同處理器實(shí)作方案。隨著實(shí)際的作業(yè)量的不同，規(guī)劃模型的工作會(huì)耗費(fèi)數(shù)分鐘到數(shù)小時(shí)。 <BR><BR> 在選擇協(xié)同處理器的組態(tài)后，會(huì)產(chǎn)生RTL層級的硬件描述以及在協(xié)同處理器上執(zhí)行的微碼指令。原始的二進(jìn)工藝序碼和微碼與通訊的驅(qū)動(dòng)程序?qū)⒁黄鸺尤胂到y(tǒng)。 <BR><BR> 架構(gòu)分析 <BR><BR> 協(xié)同處理器同步可用來快速分析不同的系統(tǒng)架構(gòu)。應(yīng)用軟件可編譯至主處理器并連結(jié)各種功能，以將其處理工作分擔(dān)給多個(gè)協(xié)同處理器。圖四顯示一個(gè)當(dāng)影片、影像及音效功能都分擔(dān)到各個(gè)處理器的系統(tǒng)范例。 <BR><BR> <IMG src="/news/upload/20071228100533515.jpg" border=0><BR><BR> 圖四：加密協(xié)同處理器架構(gòu)分析。 <BR><BR> 經(jīng)儲(chǔ)存后轉(zhuǎn)送的安全應(yīng)用提供一個(gè)協(xié)同處理器同步的實(shí)例。應(yīng)用透過網(wǎng)絡(luò)聯(lián)機(jī)會(huì)收到經(jīng)過加密的文件。經(jīng)過解密后加以檢查并加入特定的信息，最后把修改過的文件進(jìn)行加密再轉(zhuǎn)傳至下一個(gè)目的地。 <BR><BR> 本設(shè)計(jì)鎖定一個(gè)Actel M7 ProASIC3/E FPGA，此款組件內(nèi)含一個(gè)軟型ARM7TDMI核心，其內(nèi)有快閃組件的組態(tài)并嵌入額外的防護(hù)機(jī)制，以具有反制逆向工程的能力。模塊圖表如圖五所示： <BR><BR> <IMG src="/news/upload/20071228100556309.jpg" border=0><BR><BR> 圖五：儲(chǔ)存后轉(zhuǎn)送的安全架構(gòu)，以AES加密標(biāo)準(zhǔn)作初始加密算法。 <BR><BR> 一個(gè)開放原始碼的程序被編譯到ARM7核心處理器，此程序碼經(jīng)過對應(yīng)并選擇了想要分擔(dān)的加密功能。經(jīng)過同步后，協(xié)同處理器產(chǎn)生的協(xié)同候選方案如圖六所示。 <BR><BR> <IMG src="/news/upload/20071228100621853.jpg" border=0><BR><BR> 圖六：AES加密協(xié)同處理器選項(xiàng)組合。 <BR><BR> AES算法的執(zhí)行速度比原始的ARM7功能加快了3.6倍。協(xié)同處理器需要45k個(gè)邏輯閘以及21k的存儲(chǔ)器作為資料與指令的快取存儲(chǔ)器。經(jīng)常等候加密單元的處理器模塊可分擔(dān)協(xié)同處理器的加密運(yùn)算作業(yè)，讓ARM的整體處理負(fù)荷降低36%。 <BR><BR> 在設(shè)計(jì)AES協(xié)同處理器后，另一個(gè)需求就是加入支持額外加密的算法。Blowfish算法被直接編譯至AES協(xié)同處理器以提升ARM7 4.5倍的運(yùn)算速度。相較之下，針對Blowfish算法進(jìn)行同步的協(xié)同處理器，則提供加快4.7倍的加速效果。 <BR><BR> <IMG src="/news/upload/20071228100643516.jpg" border=0><BR><BR> 圖七：AES與Blowfish算法比較。 <BR><BR> 客制化發(fā)展 <BR><BR> 基本的協(xié)同處理器同步作業(yè)不需要處理器設(shè)計(jì)的專業(yè)能力。但是若想進(jìn)一步加快速度則必須在協(xié)同處理器的架構(gòu)中加入客制化的執(zhí)行單元，而軟件功能可直接對映至這些單元。在分擔(dān)這些功能的運(yùn)算負(fù)荷時(shí)，僅須定義單元界面以及基本的流量與延遲時(shí)序。同步的協(xié)同處理器將納入這些客制化單元并和它們進(jìn)行聯(lián)結(jié)。業(yè)者可分析效能方面的利益，而若有需要也可完成這些客制化單元的硬件設(shè)計(jì)。 <BR><BR></span>  <div class="rdbbtlb" id="coverDiv" class="article_reg" style="width:100%;overflow:hidden;display:none;z-index:10;position:absolute;left:0;background:#fff;"> <center> <img src="https://webstorage.eepw.com.cn/images/display/reg.jpg" border="0" usemap="#Map" /> <map name="Map" id="Map"> <area shape="rect" coords="133,235,319,253" target="_blank" /> <area shape="rect" coords="132,315,319,335" /> </map> </center> </div>  <span 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