VHDL設計的串口通信程序
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ELSE
IF (send_state 111) THEN
IF (clkbaud_tras = ’1’) THEN
txd_reg = ’0’;
state_tras = state_tras + 0001;
END IF;
ELSE
key_entry2 = ’0’;
state_tras = 0000;
END IF;
END IF;
WHEN 0001 => 發(fā)送第1位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 0010 => 發(fā)送第2位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 0011 => 發(fā)送第3位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 0100 => 發(fā)送第4位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 0101 => 發(fā)送第5位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 0110 => 發(fā)送第6位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 0111 => 發(fā)送第7位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 1000 => 發(fā)送第8位
IF (clkbaud_tras = ’1’) THEN
txd_reg = txd_buf(0);
txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1);
state_tras = state_tras + 0001;
END IF;
WHEN 1001 => 發(fā)送停止位
IF (clkbaud_tras = ’1’) THEN
txd_reg = ’1’;
txd_buf = 01010101;
state_tras = state_tras + 0001;
END IF;
WHEN 1111 =>
IF (clkbaud_tras = ’1’) THEN
state_tras = state_tras + 0001;
send_state = send_state + 001;
trasstart = ’0’;
CASE send_state IS
WHEN 000 =>
txd_buf = 01100101; e
WHEN 001 =>
txd_buf = 01101100; l
WHEN 010 =>
txd_buf = 01100011; c
WHEN 011 =>
txd_buf = 01101111; o
WHEN 100 =>
txd_buf = 01101101; m
WHEN 101 =>
txd_buf = 01100101; e
WHEN OTHERS =>
txd_buf = 00000000;
END CASE;
END IF;
WHEN OTHERS =>
IF (clkbaud_tras = ’1’) THEN
state_tras = state_tras + 0001;
trasstart = ’1’;
END IF;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(clkbaud8x,rst) 接受PC機的數據
BEGIN
IF (NOT rst = ’1’) THEN
rxd_reg1 = ’0’;
rxd_reg2 = ’0’;
rxd_buf = 00000000;
state_rec = 0000;
recstart = ’0’;
recstart_tmp = ’0’;
ELSE IF(clkbaud8x’EVENT AND clkbaud8x = ’1’) THEN
rxd_reg1 = rxd;
rxd_reg2 = rxd_reg1;
IF (state_rec = 0000) THEN
IF (recstart_tmp = ’1’) THEN
recstart = ’1’;
recstart_tmp = ’0’;
state_rec = state_rec + 0001;
ELSE
IF ((NOT rxd_reg1 AND rxd_reg2) = ’1’) THEN 檢測到起始位的下降沿，進入接受狀態(tài)
recstart_tmp = ’1’;
END IF;
END IF;
ELSE
IF (state_rec >= 0001 AND state_rec=1000) THEN
IF (clkbaud_rec = ’1’) THEN
rxd_buf(7) = rxd_reg2;
rxd_buf(6 DOWNTO 0) = rxd_buf(7 DOWNTO 1);
state_rec = state_rec + 0001;
END IF;
ELSE
IF (state_rec = 1001) THEN
IF (clkbaud_rec = ’1’) THEN
state_rec = 0000;
recstart = ’0’;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(rxd_buf) 將接受的數據用數碼管顯示出來
BEGIN
CASE rxd_buf IS
WHEN 00110000 =>
seg_data = 00000011; 0
WHEN 00110001 =>
seg_data = 10011111; 1
WHEN 00110010 =>
seg_data = 00100101; 2
WHEN 00110011 =>
seg_data = 00001101; 3
WHEN 00110100 =>
seg_data = 10011001; 4
nbs p; WHEN 00110101 =>
seg_data = 01001001; 5
WHEN 00110110 =>
seg_data = 01000001; 6
WHEN 00110111 =>
seg_data = 00011111; 7
WHEN 00111000 =>
seg_data = 00000001; 8
WHEN 00111001 =>
seg_data = 00001001; 9
WHEN 01000001 =>
seg_data = 00010001; A
WHEN 01000010 =>
seg_data = 11000001; B
WHEN 01000011 =>
seg_data = 01100011; C
WHEN 01000100 =>
seg_data = 10000101; D
WHEN 01000101 =>
seg_data = 01100001; E
WHEN 01000110 =>
seg_data = 01110001; F
WHEN OTHERS =>
seg_data = 11111111;
END CASE;
END PROCESS;
END arch;本文引用地址：http://www.ex-cimer.com/article/151790.htm
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