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          EEPW首頁 > 模擬技術(shù) > 設(shè)計(jì)應(yīng)用 > 選擇合適的系列電壓基準(zhǔn)源的絕對(duì)精度電壓輸出

          選擇合適的系列電壓基準(zhǔn)源的絕對(duì)精度電壓輸出

          作者: 時(shí)間:2012-01-30 來源:網(wǎng)絡(luò) 收藏
          /FONT>Target Error
          15625ppm
          122ppm
          977ppm
          3906 ppm
          Worst-Case Margin
          29ppm
          -62ppm
          -888ppm
          -556ppm
          Root Sum Square Margin
          7708ppm
          22ppm
          103ppm
          1326ppm

          Design A: Low Cost, Loose Accuracy

          No calibration or trimming is planned for Design A, so the MAX6102 initial error of 4000ppm (or 0.4%) directly becomes part of the budget, as does the 5250ppm due to the voltage-reference tempco (70°C × 75ppm/°C). The typical MAX6102 output-voltage temperature-hysteresis specification is also used directly in the error budget (keeping in mind that this is a typical value if we find ourselves with a design having marginal accuracy). For output-voltage long-term stability, we assume twice the MAX6102 1000-hour specification (2 × 50ppm = 100ppm), which is fairly conservative, as it's usually much better after the first 1000 hours. A conservative estimate here at least partially offsets the typical specification used for temperature hysteresis.

          To calculate the variation in reference voltage caused by load regulation, we need to know the worst-case range of currents that the voltage reference supplies to the DAC's reference input. In Step 2, we determined the maximum DAC reference current that the MAX6102 would have to drive: 140μA. The minimum current is close to 0, as the MAX5304 reference input is effectively an open circuit (several GΩ input impedance) when the DAC code value is 0. This means the total output-current variation that the MAX6102 sees is 140μA, and this value should be used for the load-regulation calculation:

          Load-Regulation Error= 140μA × 0.9mV / mA = 126μV (max)
          = 106 × 126μV / 2.5V = 50ppm (max)

          In general, it is best to be conservative and use the maximum output current directly for the load-regulation calculation. An exception may be if you're trying to extract the last bit of accuracy from a design and both the maximum and minimum DAC reference input resistance values are well specified. This approach results in a smaller load-regulation error because of the smaller ΔIREF.

          Because the power supply is specified as varying for this example, we need to consider the effects of input line regulation on the MAX6102 reference. The power-supply range is specified as 4.5V to 5.5V. From this, a conservative reference-voltage line-regulation calculation is possible:

          Line-Regulation Error= (5.5V - 4.5V) × 300μV / V = 300μV (max)
          = 106 × 300μV / 2.5V = 120ppm (max)

          The final voltage-reference-related error term to consider is the effect of reference output-noise voltage. Conveniently, Design A has a signal bandwidth (10Hz to 10kHz) that corresponds to the exact MAX6102 noise voltage bandwidth, so the wideband-noise-voltage specification of 30μVRMS is used directly (that is, bandwidth scaling is not required). Comparing the load- and line-regulation values (126μV and 300μV, respectively), we can see that noise is not a major contributor in this design. Using crude approximations to get numbers for the error analysis, we can assume an effective peak noise value of ~42μV (30μV ×√2), which corresponds to 17ppm (106 × 42μV/2.5V) with the DAC gain of 1. We are trying purposefully to keep the noise calculations simple here; a more detailed analysis can be performed if the relative error of the noise is larger or if the design is marginal. Remember that noise is specified as a typical value when judging design margin.

          We will now review the relevant MAX5304 DAC specifications that impact accuracy at or near the upper end of the code range. The DAC INL value of ±4LSB (at 10 bits) is used directly. Treating it as a single-sided quantity, as with the other error terms in our analysis, we arrive at a value of 3906ppm (106 × 4/1024). Similarly, the DAC gain error is specified as ±2LSB and results in an error of 1953ppm (106 × 2/1024). The final MAX5304 DAC specification to be considered is gain-error tempco, which gives us a typical error of 70ppm (70°C × 1ppm/°C). The DAC output noise is not specified for the MAX5304, so it is ignored, most likely without adverse consequences in this 6-bit-accurate system.

          When all of the error sources are added together, we obtain a worst-case error of 15596ppm, which just barely meets our target-error specification of 15625ppm. When confronted with this marginal situation, we can rationalize that we will probably never see an error of this magnitude, because it assumes worst-case conditions for most parameters. The root sum square (RSS) approach gives an error of 7917ppm, which is valid if the errors are uncorrelated. Some error sources may be correlated, so the truth probably lies somewhere between these two numbers. But regardless of the approach, the Design-A requirements have been met.

          Design B: High Accuracy and Precision

          The initial error of the A-grade MAX6225 is 0.04% or 400ppm, which exceeds Design B's entire 122ppm error budget. Because this application has gain calibration, virtually all of this reference initial error can be removed, assuming the calibration equipment has sufficient (~1μV) accuracy and the trim circuit has enough precision. The tempco contribution is calculated as 70ppm (70°C × 1ppm/°C), and the typical temperature hysteresis value of 20ppm is used directly. The long-term stability specification of 30ppm is also used rather than a more conservative number, because the instrument in this application has an initial burn-in as well as an annual calibration.

          Applying the same assumptions that were used in Design A, we find Design B's reference output current variation to be 140μA (coincidentally, the same number as in Design A). This l


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