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          EEPW首頁 > 光電顯示 > 設(shè)計應(yīng)用 > 設(shè)計基于LED的視頻顯示板,Designing an LED

          設(shè)計基于LED的視頻顯示板,Designing an LED

          作者: 時間:2011-12-24 來源:網(wǎng)絡(luò) 收藏
          tyle="PADDING-RIGHT: 0px; PADDING-LEFT: 0px; PADDING-BOTTOM: 0px; MARGIN: 0px; PADDING-TOP: 0px">C1C0C1C0C1C0b9b8b7b6b5b4b3b2b1b0
          Data frames, other than those containing PWM information, are also sent through the DVI interface utilizing a PC-based GUI. The data frame type is identified by corresponding circuits inside the FPGA. Data frames, other than those related to PWM information, have the format shown inTable 3, where HDR stands for header. Note that video frames for individual port PWM information do not contain a header.

          Table 3. Video-Display Reference Design, Data-Frame Screen Format
          RowLVDS 1
          Pixel 0~63
          LVDS 2
          Pixel 64~127
          LVDS 3
          Pixel 128~191
          LVDS 4
          Pixel 192~255
          LVDS 5
          Pixel 256~319
          0HDR...HDRHDR...HDRHDR...HDRHDR...HDRHDR...HDR
          1HDR...HDRHDR...HDRHDR...HDRHDR...HDRHDR...HDR
          2Chip 1 ... ...Chip 1 ... ...Chip 1 ... ...Chip 1 ... ...Chip 1 ... ...
          ... .... .... .... .... .
          ... .... .... .... .... .
          31..Chip 1920..Chip 1920..Chip 1920..Chip 1920..Chip 1920
          32HDR...HDRHDR...HDRHDR...HDRHDR...HDRHDR...HDR
          33HDR...HDRHDR...HDRHDR...HDRHDR...HDRHDR...HDR
          34Chip 1 ... ...Chip 1 ... ...Chip 1 ... ...Chip 1 ... ...Chip 1 ... ...


          關(guān)鍵詞: LED 視頻顯示板

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