具有電絕緣、線或能力和改進(jìn)噪聲限的I2C接口設(shè)計(jì)

　　本設(shè)計(jì)方案講解了一個(gè)簡單而又有效，為連接在I2C總線上的設(shè)備提供光絕緣體的方法（如圖1）。這個(gè)電路改進(jìn)了參考文獻(xiàn)1的早期版本。SDA和SCL是I²C總線的主區(qū)域；SDA1和SCL1是I²C總線的從區(qū)域。由于時(shí)鐘線是無方向性的，相當(dāng)容易實(shí)現(xiàn)主從設(shè)備間的光絕緣。P溝道MOSFET Q3提供隔離時(shí)鐘線的高速光耦I(lǐng)C2中的發(fā)光二極管電流。

圖1 電路提供由從設(shè)備到I2C總線主設(shè)備的絕緣、雙向、線或連接

　　但數(shù)據(jù)線是雙向的，且這部分電路是對(duì)稱的。電阻R6和R7是I²C總線從設(shè)備邊的上拉電阻，而R3和R1為虛上拉電 
阻，位于SDA/SCL一邊且平行于主I²C上拉電阻。如果SDA和SDA1線都為高——也就是說，沒有I²C設(shè)備使其為低——Q1將截止，沒有電流流進(jìn)光耦I(lǐng)C2的發(fā)光二極管，IC2管腳7為高，Q2截止，并且光耦I(lǐng)C1的發(fā)光二極管也截止。

　　如果有設(shè)備驅(qū)動(dòng)SDA線置低，IC2的發(fā)光二極管關(guān)閉，驅(qū)動(dòng)IC2的7管腳為低；然后二極管D2開始導(dǎo)通。結(jié)果SDA1線處于低狀態(tài)——IC2的低輸出電壓加上肖特基二極管D2的閾值電壓。在這種情況，注意到IC1的發(fā)光二極管沒有打開是重要的，因?yàn)樗鼉啥穗妷旱陀陂撝?。這意味著電路沒有鎖存，一旦SDA線被釋放，它將恢復(fù)。

　　Q3、PNP BJT（雙載子接面電晶體）和Q1有效的緩沖SDA/SCL兩條線，所以當(dāng)連接總線的開集和開漏部分I²C設(shè)備的線持續(xù)為低時(shí)，沒有額外的電流流進(jìn)。這個(gè)機(jī)構(gòu)允許電絕緣接口重復(fù)拉低提供線或能力。使用肖特基二極管D1和D2，而不是普通二極管，為的是減少總線上低狀態(tài)電壓，改進(jìn)噪聲極限。最后，由于本設(shè)計(jì)使用Fairchild半導(dǎo)體HCPL06XX設(shè)備具有低傳播延時(shí)的特征，接口沒有總線脈沖干擾問題，并且能夠以400 kHz或更高的速度工作。

　　英文原文：

　　I²C interface has galvanic isolation, wired-OR capability, improved noise margin

　　You can use optoisolators to galvanically isolate the slave devices on an I2C bus from the master device.

　　Michele Costantino, Microsaic Systems Ltd, Woking, United Kingdom; Edited by Charles H Small and Fran Granville -- EDN, 7/5/2007

　　This Design Idea describes a simple and effective way to provide optoisolation for devices connected on the I²C bus (Figure 1). It improves on an earlier version (Reference 1). SDA and SCL are on the bus master’s side of the I²C bus; SDA1 and SCL1 are on the slave device’s side. It is fairly easy to optoisolate the clock line because it is unidirectional, from the master to the slave device. A P-channel MOSFET, Q3, provides the current for the LED of the fast optocoupler, IC2, buffering the clock line.

　　The data line, however, is bidirectional. This section of the circuit is symmetrical. Resistors R6 and R7 are the I²C pullup resistors on the slave device’s side of the bus, and R3 and R1 are dummy pullups in parallel with the main I²C pullup resistors on the SDA/SCL side. If both SDA and SDA1 lines are high—that is, no I²C devices are pulling them down—Q1 is off, no current flows into the LED of optocoupler IC2, IC2’s Pin 7 is high, Q2 is off, and the LED of optocoupler IC1 is also off.

　　If a device drives the SDA line low, Q1 and the LED of IC2 turn off, driving IC2’s Pin 7 low; diode D2 then starts to conduct. The result is a low level on the SDA1 line—the low output voltage of IC2 plus the threshold voltage of Schottky barrier diode D2. In this situation, it is important to notice 
that the LED of IC1 does not turn on because the voltage applied across it is below its threshold. This situation means that the circuit does not latch, and it can recover from this state once you release the SDA line.

　　Q3 and the PNP BJT (bipolar-junction transistor), Q1, effectively buffer the two SDA/SCL lines so that no extra current flows into the open-collector and -drain stages of the I²C devices that connect to the bus when they hold the lines down. This configuration allows the optoisolated interface to repeatedly pull low, providing wired-OR capability. Using Schottky barrier diodes for D1 and D2 rather than common diodes reduces the low-level voltage on the bus, improving the noise margin. Finally, because of the low propagation-delay times of the Fairchild Semiconductor HCPL06XX devices that this design uses, this interface has no bus-glitch problems and works well at speeds of 400 kHz or higher (Reference 2).

　　References

　　Nguyen, Minh-Tam, and Martin Baumbach, “Two-wire interface has galvanic isolation,” EDN, Nov 11, 1999, pg 174.

　　Blozis, Steve, “Opto-electrical isolation of the I2C-Bus,” Embedded Systems Design, Oct 14, 2004.