Verilog模擬PS2協(xié)議的方法
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附程序，晶振頻率降至1MHz，用LED輸出鍵值
//==============================================================
module ps2(clk, rst, ps2_clk, ps2_data, data ,data2);
input clk, rst, ps2_clk , ps2_data;
output [10:0] data;
output [10:0] data2;
reg [3:0] i;
reg [10:0] data;//another fifo
reg [10:0] data2;
reg [2:0] ps2_clkr;//用一個(gè)fifo來(lái)采樣ps2_clk信號(hào)；
always @(posedge clk)
ps2_clkr = {ps2_clkr[1:0], ps2_clk};
wire ps2_clk_risingedge = (ps2_clkr[2:1]==2'b01); // now we can detect ps2_clk rising edges
wire ps2_clk_fallingedge = (ps2_clkr[2:1]==2'b10); // and falling edges
always @(posedge clk)
if(rst)
i = 0;
else
begin
if(ps2_clk_fallingedge)
begin
data2[i] = data[i];
data[i] = ps2_data;
if(i10) i = i+1;
else i = 0;
end
end
endmodule本文引用地址：http://www.ex-cimer.com/article/149372.htm
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