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          EEPW首頁 > EDA/PCB > 設(shè)計(jì)應(yīng)用 > 應(yīng)用CPLD實(shí)現(xiàn)交通控制系統(tǒng)芯片設(shè)計(jì)

          應(yīng)用CPLD實(shí)現(xiàn)交通控制系統(tǒng)芯片設(shè)計(jì)

          作者: 時間:2012-10-25 來源:網(wǎng)絡(luò) 收藏

          LIBRARY ieee;

          use ieee.STd_logic_1164.dll;

          entity traffic_control is

          PORT(

          clk :IN STD_LOGIC;

          c1,c2,3 :OUT STD_LOGIC;

          w1,w2,w3 :IN STD_LOGIC;

          r1,r2 :OUT STD_LOGIC;

          y1,y2 :OUT STD_LOGIC;

          g1.g2 :OUT STD_LOGIC;

          reset :IN STD_LOGIC);

          END traffic_control;

          ARHITECTURE a OF traffic_control IS

          TYPE STATE_SPACE IS(S0,S1,S2,S3);

          SIGNAL state:STATE_SPACE;

          BEGIN

          PROCESS(slk)

          BEGIN

          IF reset='1'THEN

          State=S0;

          ELSIF(clk EVENT AND clk='1')THEN

          CASE state IS

          WHEN S0=>

          IF w1='1'THEN

          state

          END IF;

          WHEN S1=>

          IF w2='1'THEN

          state=s2;

          END IF;

          WHEN S2=>

          IF w3='1'THEN

          State=s3;

          END IF;

          WHEN S3=>

          IF w2='1'THEN

          state=s0;

          END IF;

          END CASE;

          END IF;

          END PROCESS;

          c1='1'WHEN state=s0 ELSE'0'

          c2='1'WHEN state=S1 OR state=S3 ELSE '0'

          c3='1'WHEN state=s2 ELSE'0';

          r1='1'WHEN state=S1 OR state=S0 ELSE '0'

          y1='1'WHEN state=s3 ELSE'0';

          g1='1'WHEN state=s2 ELSE'0';

          r2='1'WHEN state=S2 OR state=S3 FLES'0';

          y2='1'WHEN state=S1 ELSE'0';

          g2='1'WHEN state=S0 ELSE'0';

          END a;



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