采用VHDL設(shè)計(jì)的全數(shù)字鎖相環(huán)電路設(shè)計(jì)

　異或門鑒相器在環(huán)路鎖定時(shí)和相位誤差達(dá)到極限時(shí)的相應(yīng)波形如圖3 所示:

　　圖3 　異或門鑒相器工作波形

　2. 2 　數(shù)字環(huán)路濾波器的設(shè)計(jì)

　　數(shù)字環(huán)路濾波器是由變?？赡嬗?jì)數(shù)器構(gòu)成的。該計(jì)數(shù)器設(shè)計(jì)為一個(gè)17 位可編程(可變模數(shù)) 可逆計(jì)數(shù)器,計(jì)數(shù)范圍是,由外部置數(shù)DCBA 控制。假設(shè)系統(tǒng)工作無相位差,由鎖相環(huán)原理知, u1 和u2 的相位差0 ,異或門鑒相器輸出是一個(gè)對(duì)稱的方波,如圖4 (a) 所示。因此可逆計(jì)數(shù)器在相同的時(shí)間間隔內(nèi)進(jìn)行加或減計(jì)數(shù),只要k 足夠大,那么從零開始的計(jì)數(shù)就不會(huì)溢出或不夠。

　　

若u1 開始落后u2 ,異或門輸出不對(duì)稱,那么計(jì)數(shù)器加計(jì)數(shù)時(shí)間比減計(jì)數(shù)時(shí)間長(zhǎng),其結(jié)果計(jì)數(shù)器隨著時(shí)間的增長(zhǎng)將溢出,產(chǎn)生一個(gè)進(jìn)位脈沖。相反,若U1 開始滯后U2 ,計(jì)數(shù)器將產(chǎn)生一個(gè)借位脈沖。進(jìn)位和借位脈沖可用來控制DCO ,使得DCO 輸出的脈沖數(shù)根據(jù)進(jìn)位和借位來加上或者是刪除一些脈沖,實(shí)際上也就改變了DCO 的輸出頻率。變模可逆計(jì)數(shù)器的設(shè)計(jì)由VHDL 完成,程序如下:

library ieee ;

use ieee. std_logic_1164. all ;

use ieee. std_logic_unsigned. all ;

entity li is

port (clk ,j ,en ,d ,c ,b ,a :in std_logic ;

r1 ,r2 :out std_logic) ;

end li ;

architecture behave of li is

signal cq ,k ,mo :std_logic_vector (16 downto 0) ;

signal cao1 ,cao2 :std_logic ;

signal instruction :std_logic_vector (3 downto 0) ;

begin

instruction = d c b a ;

with instruction select

mo ="00000000000000111"when"0001",

"00000000000001111"when"0010",

"00000000000011111"when"0011",

"00000000000111111"when"0100",

"00000000001111111"when"0101",

"00000000011111111"when"0110",

"00000000111111111"when"0111",

"00000001111111111"when"1000",

"00000011111111111"when"1001",

"00000111111111111"when"1010",

"00001111111111111"when"1011",

"00011111111111111"when"1100",

"00111111111111111"when"1101",

"01111111111111111"when"1110",

"11111111111111111"when"1111",

"00000000000000111"when others ;

process (clk ,en ,j ,k ,cq)

begin

if clk'event and clk = '1'then

k = mo ;

if en = '1'then

if j = '0'then

if cq k then cq = cq + 1 ;

else cq = (others = > '0') ;

end if ;

else

if cq > 0 then cq = cq - 1 ;

else cq = k ;

end if ;

end if ;

else cq = (others = > '0') ;

end if ;

end if ;

end process ;

process (en ,j ,cq ,k)

begin

if en = '1'then

if j = '0'then

f cq = k then cao1 = '1';

else cao1 = '0';

end if ;

cao2 = '0';

else

if cq ="00000000000000000"then

cao2 = '1';

else cao2 = '0';

end if ;

cao1 = '0';

end if ;

else cao1 = '0';cao2 = '0';

end if ;

end process ;

r1 = cao1 ; r2 = cao2 ;

end behave ;

變?？赡嬗?jì)數(shù)器(取k = 24) 的仿真波形圖如圖4 所示。

　　圖4 　變模可逆計(jì)數(shù)器(取k = 24) 的仿真波形圖